From dee82bc1e653126408f4108cd994d1e96949d064 Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Fri, 4 Aug 2017 22:49:43 +0100 Subject: ACPI: SPCR: extend XGENE 8250 workaround to m400 xgene v1/v2 chips are also used on moonshot cartridges that have different table headers to the ones on Mustang. Extend the quirk so it also recognises the Moonshot M400 variant too. Signed-off-by: Graeme Gregory Tested-by: Mark Salter Reviewed-by: Mark Salter Signed-off-by: Rafael J. Wysocki --- drivers/acpi/spcr.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'drivers/acpi/spcr.c') diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c index 98aa8c808a33..2c156941b371 100644 --- a/drivers/acpi/spcr.c +++ b/drivers/acpi/spcr.c @@ -53,17 +53,24 @@ static bool qdf2400_erratum_44_present(struct acpi_table_header *h) */ static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb) { + bool xgene_8250 = false; + if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE) return false; - if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE)) + if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) && + memcmp(tb->header.oem_id, "HPE ", ACPI_OEM_ID_SIZE)) return false; if (!memcmp(tb->header.oem_table_id, "XGENESPC", ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0) - return true; + xgene_8250 = true; - return false; + if (!memcmp(tb->header.oem_table_id, "ProLiant", + ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1) + xgene_8250 = true; + + return xgene_8250; } /** -- cgit v1.2.3 From 03c3876f2e3b4c79ced7d1d227e5a7fe645ed666 Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Fri, 4 Aug 2017 22:49:44 +0100 Subject: ACPI: SPCR: work around clock issue on xgene UART xgene v1/v2 8250 UARTs don't run at the standard clock rate expected by the driver and there is no information on clocking available from the SPCR table. As there has been no progress on relevant vendors updating DBG2/SPCR specifications to fix this work around this using the previous xgene quirk handling to avoid setting a baud rate and therefore using the UART as configured by firmware. Signed-off-by: Graeme Gregory Tested-by: Mark Salter Reviewed-by: Mark Salter Signed-off-by: Rafael J. Wysocki --- drivers/acpi/spcr.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'drivers/acpi/spcr.c') diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c index 2c156941b371..40a56b538b9f 100644 --- a/drivers/acpi/spcr.c +++ b/drivers/acpi/spcr.c @@ -188,11 +188,19 @@ int __init parse_spcr(bool earlycon) uart = "qdf2400_e44"; } - if (xgene_8250_erratum_present(table)) + if (xgene_8250_erratum_present(table)) { iotype = "mmio32"; - snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype, - table->serial_port.address, baud_rate); + /* for xgene v1 and v2 we don't know the clock rate of the + * UART so don't attempt to change to the baud rate state + * in the table because driver cannot calculate the dividers + */ + snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype, + table->serial_port.address); + } else { + snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype, + table->serial_port.address, baud_rate); + } pr_info("console: %s\n", opts); -- cgit v1.2.3