From 48c5e98fedd9e0b164df4de592fd740537ead9e2 Mon Sep 17 00:00:00 2001 From: Alex Helms Date: Mon, 12 Sep 2022 11:36:13 -0700 Subject: clk: Renesas versaclock7 ccf device driver Renesas Versaclock7 is a family of configurable clock generator ICs with fractional and integer dividers. This driver has basic support for the RC21008A device, a clock synthesizer with a crystal input and 8 outputs. The supports changing the FOD and IOD rates, and each output can be gated. Signed-off-by: Alex Helms Link: https://lore.kernel.org/r/20220912183613.22213-3-alexander.helms.jy@renesas.com Tested-by: Saeed Nowshadi Signed-off-by: Stephen Boyd --- drivers/clk/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/Makefile') diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d5db170d38d2..e3ca0d058a25 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o +obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o -- cgit v1.2.3