From 723e367114dec95abe8bba4118c4c7c3542a463f Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Mon, 23 May 2022 17:33:34 +0800 Subject: clk: mediatek: reset: Support nonsequence base offsets of reset registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt2701.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers/clk/mediatek/clk-mt2701.c') diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index f165126232d3..6c7a80fb4349 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -735,18 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; +static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = pericfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), }, }; -- cgit v1.2.3