From 62782ba856d1c89c03535e92c32c997e1ebfed0b Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Mon, 22 Nov 2021 01:27:39 +0200 Subject: clk: samsung: exynos850: Implement CMU_CMGP domain CMU_CMGP clock domain provides clocks for CMGP IP-core (Common GPIO). CMGP module encapsulates next blocks: - 8 GPIO lines - 1 GPADC - 2 USI blocks, each can be configured to provide one of UART/SPI/HSI2C serial interfaces Signed-off-by: Sam Protsenko Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20211121232741.6967-5-semen.protsenko@linaro.org --- drivers/clk/samsung/clk-exynos850.c | 100 ++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) (limited to 'drivers/clk/samsung/clk-exynos850.c') diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index 95e373d17b42..0eab7a115b44 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -492,6 +492,103 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = { .clk_name = "dout_clkcmu_apm_bus", }; +/* ---- CMU_CMGP ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_CMGP (0x11c00000) */ +#define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 +#define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 +#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c +#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 +#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 + +static const unsigned long cmgp_clk_regs[] __initconst = { + CLK_CON_MUX_CLK_CMGP_ADC, + CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, + CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, + CLK_CON_DIV_DIV_CLK_CMGP_ADC, + CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, + CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, + CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, + CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, + CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, +}; + +/* List of parent clocks for Muxes in CMU_CMGP */ +PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; +PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; +PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; + +static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { + FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), +}; + +static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { + MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, + CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), + MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), + MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), +}; + +static const struct samsung_div_clock cmgp_div_clks[] __initconst = { + DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", + CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), + DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", + CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), + DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", + CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), +}; + +static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { + GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", + "gout_clkcmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), + GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", + "gout_clkcmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), + GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", + "gout_clkcmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, 0, 0), + GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", + CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), + GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", + "gout_clkcmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), + GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", + CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), + GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", + "gout_clkcmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), +}; + +static const struct samsung_cmu_info cmgp_cmu_info __initconst = { + .mux_clks = cmgp_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), + .div_clks = cmgp_div_clks, + .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), + .gate_clks = cmgp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), + .fixed_clks = cmgp_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), + .nr_clk_ids = CMGP_NR_CLK, + .clk_regs = cmgp_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), + .clk_name = "gout_clkcmu_cmgp_bus", +}; + /* ---- CMU_HSI ------------------------------------------------------------- */ /* Register Offset definitions for CMU_HSI (0x13400000) */ @@ -943,6 +1040,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = { { .compatible = "samsung,exynos850-cmu-apm", .data = &apm_cmu_info, + }, { + .compatible = "samsung,exynos850-cmu-cmgp", + .data = &cmgp_cmu_info, }, { .compatible = "samsung,exynos850-cmu-hsi", .data = &hsi_cmu_info, -- cgit v1.2.3