From 6f15b178cd6315c997981f76c6ebed7ad39144c5 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Thu, 5 Oct 2023 15:42:42 +0530 Subject: EDAC/versal: Add a Xilinx Versal memory controller driver Add a EDAC driver for the RAS capabilities on the Xilinx integrated DDR Memory Controllers (DDRMCs) which support both DDR4 and LPDDR4/4X memory interfaces. It has four programmable Network-on-Chip (NoC) interface ports and is designed to handle multiple streams of traffic. The driver reports correctable and uncorrectable errors, and also creates debugfs entries for testing through error injection. [ bp: - Add a pointer to the documentation about the register unlock code. - Squash in a fix for a Smatch static checker issue as reported by Dan Carpenter: https://lore.kernel.org/r/a4db6f93-8e5f-4d55-a7b8-b5a987d48a58@moroto.mountain ] Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Signed-off-by: Shubhrajyoti Datta Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20231005101242.14621-3-shubhrajyoti.datta@amd.com --- drivers/edac/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/edac/Kconfig') diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 110e99b86a66..5a7f3fabee22 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -561,4 +561,16 @@ config EDAC_NPCM error detection (in-line ECC in which a section 1/8th of the memory device used to store data is used for ECC storage). +config EDAC_VERSAL + tristate "Xilinx Versal DDR Memory Controller" + depends on ARCH_ZYNQMP || COMPILE_TEST + help + Support for error detection and correction on the Xilinx Versal DDR + memory controller. + + Report both single bit errors (CE) and double bit errors (UE). + Support injecting both correctable and uncorrectable errors + for debugging purposes. + + endif # EDAC -- cgit v1.2.3