From 7f6998a41257a8930ee5b6866ba56a25230841ed Mon Sep 17 00:00:00 2001 From: Jan Luebbe Date: Fri, 12 Jul 2019 05:46:57 +0100 Subject: ARM: 8888/1: EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC Add support for the ECC functionality as found in the DDR RAM and L2 cache controllers on the MV78230/MV78x60 SoCs. This driver has been tested on the MV78460 (on a custom board with a DDR3 ECC DIMM). [cp use SPDX license] Signed-off-by: Jan Luebbe Signed-off-by: Chris Packham Reviewed-by: Borislav Petkov Signed-off-by: Russell King --- drivers/edac/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/edac/Kconfig') diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 200c04ce5b0e..39c58b37b889 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -466,6 +466,13 @@ config EDAC_SIFIVE help Support for error detection and correction on the SiFive SoCs. +config EDAC_ARMADA_XP + bool "Marvell Armada XP DDR and L2 Cache ECC" + depends on MACH_MVEBU_V7 + help + Support for error correction and detection on the Marvell Aramada XP + DDR RAM and L2 cache controllers. + config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" depends on ARCH_ZYNQ || ARCH_ZYNQMP -- cgit v1.2.3