From d2c19e89e03cced2417175f48586648ae88f7cbf Mon Sep 17 00:00:00 2001 From: Pandith N Date: Thu, 16 Feb 2023 18:53:54 +0530 Subject: gpio: tangier: Introduce Intel Tangier GPIO driver Intel Elkhart Lake and Merrifield platforms have same GPIO IP. Intel Tangier implements the common GPIO functionalities for both Elkhart Lake and Merrifield platforms. Signed-off-by: Pandith N Co-developed-by: Raag Jadav Signed-off-by: Raag Jadav Co-developed-by: Andy Shevchenko Signed-off-by: Andy Shevchenko --- drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-tangier.c | 536 ++++++++++++++++++++++++++++++++++++++++++++ drivers/gpio/gpio-tangier.h | 107 +++++++++ 4 files changed, 652 insertions(+) create mode 100644 drivers/gpio/gpio-tangier.c create mode 100644 drivers/gpio/gpio-tangier.h (limited to 'drivers/gpio') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2b72a7a7084a..d9c27e733e01 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -619,6 +619,14 @@ config GPIO_SYSCON help Say yes here to support GPIO functionality though SYSCON driver. +config GPIO_TANGIER + tristate + select GPIOLIB_IRQCHIP + help + GPIO support for Intel Tangier and compatible platforms. + + If built as a module its name will be gpio-tangier. + config GPIO_TB10X bool select GPIO_GENERIC diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c048ba003367..d884abbf6156 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -145,6 +145,7 @@ obj-$(CONFIG_GPIO_SPRD) += gpio-sprd.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o obj-$(CONFIG_GPIO_SYSCON) += gpio-syscon.o +obj-$(CONFIG_GPIO_TANGIER) += gpio-tangier.o obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o obj-$(CONFIG_GPIO_TEGRA186) += gpio-tegra186.o diff --git a/drivers/gpio/gpio-tangier.c b/drivers/gpio/gpio-tangier.c new file mode 100644 index 000000000000..e990781935ba --- /dev/null +++ b/drivers/gpio/gpio-tangier.c @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Tangier GPIO driver + * + * Copyright (c) 2016, 2021, 2023 Intel Corporation. + * + * Authors: Andy Shevchenko + * Pandith N + * Raag Jadav + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "gpio-tangier.h" + +#define GCCR 0x000 /* Controller configuration */ +#define GPLR 0x004 /* Pin level r/o */ +#define GPDR 0x01c /* Pin direction */ +#define GPSR 0x034 /* Pin set w/o */ +#define GPCR 0x04c /* Pin clear w/o */ +#define GRER 0x064 /* Rising edge detect */ +#define GFER 0x07c /* Falling edge detect */ +#define GFBR 0x094 /* Glitch filter bypass */ +#define GIMR 0x0ac /* Interrupt mask */ +#define GISR 0x0c4 /* Interrupt source */ +#define GITR 0x300 /* Input type */ +#define GLPR 0x318 /* Level input polarity */ + +/** + * struct tng_gpio_context - Context to be saved during suspend-resume + * @level: Pin level + * @gpdr: Pin direction + * @grer: Rising edge detect enable + * @gfer: Falling edge detect enable + * @gimr: Interrupt mask + * @gwmr: Wake mask + */ +struct tng_gpio_context { + u32 level; + u32 gpdr; + u32 grer; + u32 gfer; + u32 gimr; + u32 gwmr; +}; + +static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, + unsigned int reg) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + u8 reg_offset = offset / 32; + + return priv->reg_base + reg + reg_offset * 4; +} + +static void __iomem *gpio_reg_and_bit(struct gpio_chip *chip, unsigned int offset, + unsigned int reg, u8 *bit) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + u8 reg_offset = offset / 32; + u8 shift = offset % 32; + + *bit = shift; + return priv->reg_base + reg + reg_offset * 4; +} + +static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + void __iomem *gplr; + u8 shift; + + gplr = gpio_reg_and_bit(chip, offset, GPLR, &shift); + + return !!(readl(gplr) & BIT(shift)); +} + +static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *reg; + u8 shift; + + reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift); + + raw_spin_lock_irqsave(&priv->lock, flags); + + writel(BIT(shift), reg); + + raw_spin_unlock_irqrestore(&priv->lock, flags); +} + +static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *gpdr; + u32 value; + u8 shift; + + gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(gpdr); + value &= ~BIT(shift); + writel(value, gpdr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *gpdr; + u8 shift; + + gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); + tng_gpio_set(chip, offset, value); + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(gpdr); + value |= BIT(shift); + writel(value, gpdr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int tng_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + void __iomem *gpdr; + u8 shift; + + gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); + + if (readl(gpdr) & BIT(shift)) + return GPIO_LINE_DIRECTION_OUT; + + return GPIO_LINE_DIRECTION_IN; +} + +static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, + unsigned int debounce) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *gfbr; + u32 value; + u8 shift; + + gfbr = gpio_reg_and_bit(chip, offset, GFBR, &shift); + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(gfbr); + if (debounce) + value &= ~BIT(shift); + else + value |= BIT(shift); + writel(value, gfbr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int tng_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + u32 debounce; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + return gpiochip_generic_config(chip, offset, config); + case PIN_CONFIG_INPUT_DEBOUNCE: + debounce = pinconf_to_config_argument(config); + return tng_gpio_set_debounce(chip, offset, debounce); + default: + return -ENOTSUPP; + } +} + +static void tng_irq_ack(struct irq_data *d) +{ + struct tng_gpio *priv = irq_data_get_irq_chip_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + unsigned long flags; + void __iomem *gisr; + u8 shift; + + gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift); + + raw_spin_lock_irqsave(&priv->lock, flags); + writel(BIT(shift), gisr); + raw_spin_unlock_irqrestore(&priv->lock, flags); +} + +static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask) +{ + unsigned long flags; + void __iomem *gimr; + u32 value; + u8 shift; + + gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift); + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(gimr); + if (unmask) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, gimr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); +} + +static void tng_irq_mask(struct irq_data *d) +{ + struct tng_gpio *priv = irq_data_get_irq_chip_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + + tng_irq_unmask_mask(priv, gpio, false); + gpiochip_disable_irq(&priv->chip, gpio); +} + +static void tng_irq_unmask(struct irq_data *d) +{ + struct tng_gpio *priv = irq_data_get_irq_chip_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + + gpiochip_enable_irq(&priv->chip, gpio); + tng_irq_unmask_mask(priv, gpio, true); +} + +static int tng_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct tng_gpio *priv = gpiochip_get_data(gc); + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); + void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); + void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); + void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); + u8 shift = gpio % 32; + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(grer); + if (type & IRQ_TYPE_EDGE_RISING) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, grer); + + value = readl(gfer); + if (type & IRQ_TYPE_EDGE_FALLING) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, gfer); + + /* + * To prevent glitches from triggering an unintended level interrupt, + * configure GLPR register first and then configure GITR. + */ + value = readl(glpr); + if (type & IRQ_TYPE_LEVEL_LOW) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, glpr); + + if (type & IRQ_TYPE_LEVEL_MASK) { + value = readl(gitr); + value |= BIT(shift); + writel(value, gitr); + + irq_set_handler_locked(d, handle_level_irq); + } else if (type & IRQ_TYPE_EDGE_BOTH) { + value = readl(gitr); + value &= ~BIT(shift); + writel(value, gitr); + + irq_set_handler_locked(d, handle_edge_irq); + } + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int tng_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct tng_gpio *priv = gpiochip_get_data(gc); + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwmr); + void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwsr); + u8 shift = gpio % 32; + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&priv->lock, flags); + + /* Clear the existing wake status */ + writel(BIT(shift), gwsr); + + value = readl(gwmr); + if (on) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, gwmr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio); + return 0; +} + +static const struct irq_chip tng_irqchip = { + .name = "gpio-tangier", + .irq_ack = tng_irq_ack, + .irq_mask = tng_irq_mask, + .irq_unmask = tng_irq_unmask, + .irq_set_type = tng_irq_set_type, + .irq_set_wake = tng_irq_set_wake, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void tng_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct tng_gpio *priv = gpiochip_get_data(gc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); + unsigned long base, gpio; + + chained_irq_enter(irqchip, desc); + + /* Check GPIO controller to check which pin triggered the interrupt */ + for (base = 0; base < priv->chip.ngpio; base += 32) { + void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); + void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); + unsigned long pending, enabled; + + pending = readl(gisr); + enabled = readl(gimr); + + /* Only interrupts that are enabled */ + pending &= enabled; + + for_each_set_bit(gpio, &pending, 32) + generic_handle_domain_irq(gc->irq.domain, base + gpio); + } + + chained_irq_exit(irqchip, desc); +} + +static int tng_irq_init_hw(struct gpio_chip *chip) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + void __iomem *reg; + unsigned int base; + + for (base = 0; base < priv->chip.ngpio; base += 32) { + /* Clear the rising-edge detect register */ + reg = gpio_reg(&priv->chip, base, GRER); + writel(0, reg); + + /* Clear the falling-edge detect register */ + reg = gpio_reg(&priv->chip, base, GFER); + writel(0, reg); + } + + return 0; +} + +static int tng_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + const struct tng_gpio_pinrange *range; + unsigned int i; + int ret; + + for (i = 0; i < priv->pin_info.nranges; i++) { + range = &priv->pin_info.pin_ranges[i]; + ret = gpiochip_add_pin_range(&priv->chip, + priv->pin_info.name, + range->gpio_base, + range->pin_base, + range->npins); + if (ret) { + dev_err(priv->dev, "failed to add GPIO pin range\n"); + return ret; + } + } + + return 0; +} + +int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio) +{ + const struct tng_gpio_info *info = &gpio->info; + struct gpio_irq_chip *girq; + int ret; + + gpio->ctx = devm_kcalloc(dev, DIV_ROUND_UP(info->ngpio, 32), sizeof(*gpio->ctx), GFP_KERNEL); + if (!gpio->ctx) + return -ENOMEM; + + gpio->chip.label = dev_name(dev); + gpio->chip.parent = dev; + gpio->chip.request = gpiochip_generic_request; + gpio->chip.free = gpiochip_generic_free; + gpio->chip.direction_input = tng_gpio_direction_input; + gpio->chip.direction_output = tng_gpio_direction_output; + gpio->chip.get = tng_gpio_get; + gpio->chip.set = tng_gpio_set; + gpio->chip.get_direction = tng_gpio_get_direction; + gpio->chip.set_config = tng_gpio_set_config; + gpio->chip.base = info->base; + gpio->chip.ngpio = info->ngpio; + gpio->chip.can_sleep = false; + gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges; + + raw_spin_lock_init(&gpio->lock); + + girq = &gpio->chip.irq; + gpio_irq_chip_set_chip(girq, &tng_irqchip); + girq->init_hw = tng_irq_init_hw; + girq->parent_handler = tng_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, girq->num_parents, + sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + + girq->parents[0] = gpio->irq; + girq->first = info->first; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio); + if (ret) + return dev_err_probe(dev, ret, "gpiochip_add error\n"); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(devm_tng_gpio_probe, GPIO_TANGIER); + +int tng_gpio_suspend(struct device *dev) +{ + struct tng_gpio *priv = dev_get_drvdata(dev); + struct tng_gpio_context *ctx = priv->ctx; + unsigned long flags; + unsigned int base; + + raw_spin_lock_irqsave(&priv->lock, flags); + + for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { + /* GPLR is RO, values read will be restored using GPSR */ + ctx->level = readl(gpio_reg(&priv->chip, base, GPLR)); + + ctx->gpdr = readl(gpio_reg(&priv->chip, base, GPDR)); + ctx->grer = readl(gpio_reg(&priv->chip, base, GRER)); + ctx->gfer = readl(gpio_reg(&priv->chip, base, GFER)); + ctx->gimr = readl(gpio_reg(&priv->chip, base, GIMR)); + + ctx->gwmr = readl(gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); + } + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(tng_gpio_suspend, GPIO_TANGIER); + +int tng_gpio_resume(struct device *dev) +{ + struct tng_gpio *priv = dev_get_drvdata(dev); + struct tng_gpio_context *ctx = priv->ctx; + unsigned long flags; + unsigned int base; + + raw_spin_lock_irqsave(&priv->lock, flags); + + for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { + /* GPLR is RO, values read will be restored using GPSR */ + writel(ctx->level, gpio_reg(&priv->chip, base, GPSR)); + + writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR)); + writel(ctx->grer, gpio_reg(&priv->chip, base, GRER)); + writel(ctx->gfer, gpio_reg(&priv->chip, base, GFER)); + writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR)); + + writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); + } + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(tng_gpio_resume, GPIO_TANGIER); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Raag Jadav "); +MODULE_DESCRIPTION("Intel Tangier GPIO driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpio/gpio-tangier.h b/drivers/gpio/gpio-tangier.h new file mode 100644 index 000000000000..dd3df3c3f5c6 --- /dev/null +++ b/drivers/gpio/gpio-tangier.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel Tangier GPIO functions + * + * Copyright (c) 2016, 2021, 2023 Intel Corporation. + * + * Authors: Andy Shevchenko + * Pandith N + * Raag Jadav + */ + +#ifndef _GPIO_TANGIER_H_ +#define _GPIO_TANGIER_H_ + +#include +#include +#include + +struct device; + +struct tng_gpio_context; + +/** + * struct tng_wake_regs - Platform specific wake registers + * @gwmr: Wake mask + * @gwsr: Wake source + * @gsir: Secure input + */ +struct tng_wake_regs { + u32 gwmr; + u32 gwsr; + u32 gsir; +}; + +/** + * struct tng_gpio_pinrange - Map pin numbers to gpio numbers + * @gpio_base: Starting GPIO number of this range + * @pin_base: Starting pin number of this range + * @npins: Number of pins in this range + */ +struct tng_gpio_pinrange { + unsigned int gpio_base; + unsigned int pin_base; + unsigned int npins; +}; + +#define GPIO_PINRANGE(gstart, gend, pstart) \ +(struct tng_gpio_pinrange) { \ + .gpio_base = (gstart), \ + .pin_base = (pstart), \ + .npins = (gend) - (gstart) + 1, \ + } + +/** + * struct tng_gpio_pin_info - Platform specific pinout information + * @pin_ranges: Pin to GPIO mapping + * @nranges: Number of pin ranges + * @name: Respective pinctrl device name + */ +struct tng_gpio_pin_info { + const struct tng_gpio_pinrange *pin_ranges; + unsigned int nranges; + const char *name; +}; + +/** + * struct tng_gpio_info - Platform specific GPIO and IRQ information + * @base: GPIO base to start numbering with + * @ngpio: Amount of GPIOs supported by the controller + * @first: First IRQ to start numbering with + */ +struct tng_gpio_info { + int base; + u16 ngpio; + unsigned int first; +}; + +/** + * struct tng_gpio - Platform specific private data + * @chip: Instance of the struct gpio_chip + * @reg_base: Base address of MMIO registers + * @irq: Interrupt for the GPIO device + * @lock: Synchronization lock to prevent I/O race conditions + * @dev: The GPIO device + * @ctx: Context to be saved during suspend-resume + * @wake_regs: Platform specific wake registers + * @pin_info: Platform specific pinout information + * @info: Platform specific GPIO and IRQ information + */ +struct tng_gpio { + struct gpio_chip chip; + void __iomem *reg_base; + int irq; + raw_spinlock_t lock; + struct device *dev; + struct tng_gpio_context *ctx; + struct tng_wake_regs wake_regs; + struct tng_gpio_pin_info pin_info; + struct tng_gpio_info info; +}; + +int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio); + +int tng_gpio_suspend(struct device *dev); +int tng_gpio_resume(struct device *dev); + +#endif /* _GPIO_TANGIER_H_ */ -- cgit v1.2.3 From 34840be53410c29d67ffb304588a258fab785fd7 Mon Sep 17 00:00:00 2001 From: Pandith N Date: Thu, 16 Feb 2023 20:34:19 +0200 Subject: gpio: merrifield: Adapt to Intel Tangier GPIO driver Make use of Intel Tangier GPIO as a library driver for Merrifield. Signed-off-by: Pandith N Co-developed-by: Raag Jadav Signed-off-by: Raag Jadav Co-developed-by: Andy Shevchenko Signed-off-by: Andy Shevchenko --- drivers/gpio/Kconfig | 4 +- drivers/gpio/gpio-merrifield.c | 440 +++-------------------------------------- drivers/gpio/gpio-tangier.h | 5 + 3 files changed, 34 insertions(+), 415 deletions(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d9c27e733e01..c769d29315e5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -624,6 +624,8 @@ config GPIO_TANGIER select GPIOLIB_IRQCHIP help GPIO support for Intel Tangier and compatible platforms. + Currently supported: + - Merrifield If built as a module its name will be gpio-tangier. @@ -1516,7 +1518,7 @@ config GPIO_BT8XX config GPIO_MERRIFIELD tristate "Intel Merrifield GPIO support" depends on X86_INTEL_MID - select GPIOLIB_IRQCHIP + select GPIO_TANGIER help Say Y here to support Intel Merrifield GPIO. diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c index 92ea8411050d..5c0b460fcd90 100644 --- a/drivers/gpio/gpio-merrifield.c +++ b/drivers/gpio/gpio-merrifield.c @@ -2,60 +2,25 @@ /* * Intel Merrifield SoC GPIO driver * - * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2016, 2023 Intel Corporation. * Author: Andy Shevchenko */ #include #include -#include -#include +#include +#include #include #include #include -#include -#include +#include -#define GCCR 0x000 /* controller configuration */ -#define GPLR 0x004 /* pin level r/o */ -#define GPDR 0x01c /* pin direction */ -#define GPSR 0x034 /* pin set w/o */ -#define GPCR 0x04c /* pin clear w/o */ -#define GRER 0x064 /* rising edge detect */ -#define GFER 0x07c /* falling edge detect */ -#define GFBR 0x094 /* glitch filter bypass */ -#define GIMR 0x0ac /* interrupt mask */ -#define GISR 0x0c4 /* interrupt source */ -#define GITR 0x300 /* input type */ -#define GLPR 0x318 /* level input polarity */ -#define GWMR 0x400 /* wake mask */ -#define GWSR 0x418 /* wake source */ -#define GSIR 0xc00 /* secure input */ +#include "gpio-tangier.h" /* Intel Merrifield has 192 GPIO pins */ #define MRFLD_NGPIO 192 -struct mrfld_gpio_pinrange { - unsigned int gpio_base; - unsigned int pin_base; - unsigned int npins; -}; - -#define GPIO_PINRANGE(gstart, gend, pstart) \ - { \ - .gpio_base = (gstart), \ - .pin_base = (pstart), \ - .npins = (gend) - (gstart) + 1, \ - } - -struct mrfld_gpio { - struct gpio_chip chip; - void __iomem *reg_base; - raw_spinlock_t lock; - struct device *dev; -}; - -static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = { +static const struct tng_gpio_pinrange mrfld_gpio_ranges[] = { GPIO_PINRANGE(0, 11, 146), GPIO_PINRANGE(12, 13, 144), GPIO_PINRANGE(14, 15, 35), @@ -84,316 +49,7 @@ static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = { GPIO_PINRANGE(190, 191, 178), }; -static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, - unsigned int reg_type_offset) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - u8 reg = offset / 32; - - return priv->reg_base + reg_type_offset + reg * 4; -} - -static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - void __iomem *gplr = gpio_reg(chip, offset, GPLR); - - return !!(readl(gplr) & BIT(offset % 32)); -} - -static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *gpsr, *gpcr; - unsigned long flags; - - raw_spin_lock_irqsave(&priv->lock, flags); - - if (value) { - gpsr = gpio_reg(chip, offset, GPSR); - writel(BIT(offset % 32), gpsr); - } else { - gpcr = gpio_reg(chip, offset, GPCR); - writel(BIT(offset % 32), gpcr); - } - - raw_spin_unlock_irqrestore(&priv->lock, flags); -} - -static int mrfld_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *gpdr = gpio_reg(chip, offset, GPDR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - value = readl(gpdr); - value &= ~BIT(offset % 32); - writel(value, gpdr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -static int mrfld_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *gpdr = gpio_reg(chip, offset, GPDR); - unsigned long flags; - - mrfld_gpio_set(chip, offset, value); - - raw_spin_lock_irqsave(&priv->lock, flags); - - value = readl(gpdr); - value |= BIT(offset % 32); - writel(value, gpdr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) -{ - void __iomem *gpdr = gpio_reg(chip, offset, GPDR); - - if (readl(gpdr) & BIT(offset % 32)) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, - unsigned int debounce) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *gfbr = gpio_reg(chip, offset, GFBR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - if (debounce) - value = readl(gfbr) & ~BIT(offset % 32); - else - value = readl(gfbr) | BIT(offset % 32); - writel(value, gfbr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset, - unsigned long config) -{ - u32 debounce; - - if ((pinconf_to_config_param(config) == PIN_CONFIG_BIAS_DISABLE) || - (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_UP) || - (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_DOWN)) - return gpiochip_generic_config(chip, offset, config); - - if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) - return -ENOTSUPP; - - debounce = pinconf_to_config_argument(config); - return mrfld_gpio_set_debounce(chip, offset, debounce); -} - -static void mrfld_irq_ack(struct irq_data *d) -{ - struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); - u32 gpio = irqd_to_hwirq(d); - void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR); - unsigned long flags; - - raw_spin_lock_irqsave(&priv->lock, flags); - - writel(BIT(gpio % 32), gisr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); -} - -static void mrfld_irq_unmask_mask(struct mrfld_gpio *priv, u32 gpio, bool unmask) -{ - void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - if (unmask) - value = readl(gimr) | BIT(gpio % 32); - else - value = readl(gimr) & ~BIT(gpio % 32); - writel(value, gimr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); -} - -static void mrfld_irq_mask(struct irq_data *d) -{ - struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); - u32 gpio = irqd_to_hwirq(d); - - mrfld_irq_unmask_mask(priv, gpio, false); - gpiochip_disable_irq(&priv->chip, gpio); -} - -static void mrfld_irq_unmask(struct irq_data *d) -{ - struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); - u32 gpio = irqd_to_hwirq(d); - - gpiochip_enable_irq(&priv->chip, gpio); - mrfld_irq_unmask_mask(priv, gpio, true); -} - -static int mrfld_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct mrfld_gpio *priv = gpiochip_get_data(gc); - u32 gpio = irqd_to_hwirq(d); - void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); - void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); - void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); - void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - if (type & IRQ_TYPE_EDGE_RISING) - value = readl(grer) | BIT(gpio % 32); - else - value = readl(grer) & ~BIT(gpio % 32); - writel(value, grer); - - if (type & IRQ_TYPE_EDGE_FALLING) - value = readl(gfer) | BIT(gpio % 32); - else - value = readl(gfer) & ~BIT(gpio % 32); - writel(value, gfer); - - /* - * To prevent glitches from triggering an unintended level interrupt, - * configure GLPR register first and then configure GITR. - */ - if (type & IRQ_TYPE_LEVEL_LOW) - value = readl(glpr) | BIT(gpio % 32); - else - value = readl(glpr) & ~BIT(gpio % 32); - writel(value, glpr); - - if (type & IRQ_TYPE_LEVEL_MASK) { - value = readl(gitr) | BIT(gpio % 32); - writel(value, gitr); - - irq_set_handler_locked(d, handle_level_irq); - } else if (type & IRQ_TYPE_EDGE_BOTH) { - value = readl(gitr) & ~BIT(gpio % 32); - writel(value, gitr); - - irq_set_handler_locked(d, handle_edge_irq); - } - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct mrfld_gpio *priv = gpiochip_get_data(gc); - u32 gpio = irqd_to_hwirq(d); - void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR); - void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - /* Clear the existing wake status */ - writel(BIT(gpio % 32), gwsr); - - if (on) - value = readl(gwmr) | BIT(gpio % 32); - else - value = readl(gwmr) & ~BIT(gpio % 32); - writel(value, gwmr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - dev_dbg(priv->dev, "%s wake for gpio %u\n", str_enable_disable(on), gpio); - return 0; -} - -static const struct irq_chip mrfld_irqchip = { - .name = "gpio-merrifield", - .irq_ack = mrfld_irq_ack, - .irq_mask = mrfld_irq_mask, - .irq_unmask = mrfld_irq_unmask, - .irq_set_type = mrfld_irq_set_type, - .irq_set_wake = mrfld_irq_set_wake, - .flags = IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, -}; - -static void mrfld_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct mrfld_gpio *priv = gpiochip_get_data(gc); - struct irq_chip *irqchip = irq_desc_get_chip(desc); - unsigned long base, gpio; - - chained_irq_enter(irqchip, desc); - - /* Check GPIO controller to check which pin triggered the interrupt */ - for (base = 0; base < priv->chip.ngpio; base += 32) { - void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); - void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); - unsigned long pending, enabled; - - pending = readl(gisr); - enabled = readl(gimr); - - /* Only interrupts that are enabled */ - pending &= enabled; - - for_each_set_bit(gpio, &pending, 32) - generic_handle_domain_irq(gc->irq.domain, base + gpio); - } - - chained_irq_exit(irqchip, desc); -} - -static int mrfld_irq_init_hw(struct gpio_chip *chip) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *reg; - unsigned int base; - - for (base = 0; base < priv->chip.ngpio; base += 32) { - /* Clear the rising-edge detect register */ - reg = gpio_reg(&priv->chip, base, GRER); - writel(0, reg); - /* Clear the falling-edge detect register */ - reg = gpio_reg(&priv->chip, base, GFER); - writel(0, reg); - } - - return 0; -} - -static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv) +static const char *mrfld_gpio_get_pinctrl_dev_name(struct tng_gpio *priv) { struct acpi_device *adev; const char *name; @@ -409,37 +65,10 @@ static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv) return name; } -static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - const struct mrfld_gpio_pinrange *range; - const char *pinctrl_dev_name; - unsigned int i; - int retval; - - pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv); - if (!pinctrl_dev_name) - return -ENOMEM; - - for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) { - range = &mrfld_gpio_ranges[i]; - retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name, - range->gpio_base, - range->pin_base, - range->npins); - if (retval) { - dev_err(priv->dev, "failed to add GPIO pin range\n"); - return retval; - } - } - - return 0; -} - static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id) { - struct gpio_irq_chip *girq; - struct mrfld_gpio *priv; + struct device *dev = &pdev->dev; + struct tng_gpio *priv; u32 gpio_base, irq_base; void __iomem *base; int retval; @@ -469,46 +98,29 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id priv->dev = &pdev->dev; priv->reg_base = pcim_iomap_table(pdev)[0]; - priv->chip.label = dev_name(&pdev->dev); - priv->chip.parent = &pdev->dev; - priv->chip.request = gpiochip_generic_request; - priv->chip.free = gpiochip_generic_free; - priv->chip.direction_input = mrfld_gpio_direction_input; - priv->chip.direction_output = mrfld_gpio_direction_output; - priv->chip.get = mrfld_gpio_get; - priv->chip.set = mrfld_gpio_set; - priv->chip.get_direction = mrfld_gpio_get_direction; - priv->chip.set_config = mrfld_gpio_set_config; - priv->chip.base = gpio_base; - priv->chip.ngpio = MRFLD_NGPIO; - priv->chip.can_sleep = false; - priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges; + priv->pin_info.pin_ranges = mrfld_gpio_ranges; + priv->pin_info.nranges = ARRAY_SIZE(mrfld_gpio_ranges); + priv->pin_info.name = mrfld_gpio_get_pinctrl_dev_name(priv); + if (!priv->pin_info.name) + return -ENOMEM; - raw_spin_lock_init(&priv->lock); + priv->info.base = gpio_base; + priv->info.ngpio = MRFLD_NGPIO; + priv->info.first = irq_base; retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); if (retval < 0) return retval; - girq = &priv->chip.irq; - gpio_irq_chip_set_chip(girq, &mrfld_irqchip); - girq->init_hw = mrfld_irq_init_hw; - girq->parent_handler = mrfld_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, - sizeof(*girq->parents), GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] = pci_irq_vector(pdev, 0); - girq->first = irq_base; - girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_bad_irq; + priv->irq = pci_irq_vector(pdev, 0); - retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); - if (retval) { - dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); - return retval; - } + priv->wake_regs.gwmr = GWMR_MRFLD; + priv->wake_regs.gwsr = GWSR_MRFLD; + priv->wake_regs.gsir = GSIR_MRFLD; + + retval = devm_tng_gpio_probe(dev, priv); + if (retval) + return dev_err_probe(dev, retval, "tng_gpio_probe error\n"); pci_set_drvdata(pdev, priv); return 0; @@ -525,9 +137,9 @@ static struct pci_driver mrfld_gpio_driver = { .id_table = mrfld_gpio_ids, .probe = mrfld_gpio_probe, }; - module_pci_driver(mrfld_gpio_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(GPIO_TANGIER); diff --git a/drivers/gpio/gpio-tangier.h b/drivers/gpio/gpio-tangier.h index dd3df3c3f5c6..735b966db423 100644 --- a/drivers/gpio/gpio-tangier.h +++ b/drivers/gpio/gpio-tangier.h @@ -20,6 +20,11 @@ struct device; struct tng_gpio_context; +/* Merrifield specific wake registers */ +#define GWMR_MRFLD 0x400 /* Wake mask */ +#define GWSR_MRFLD 0x418 /* Wake source */ +#define GSIR_MRFLD 0xc00 /* Secure input */ + /** * struct tng_wake_regs - Platform specific wake registers * @gwmr: Wake mask -- cgit v1.2.3 From dd0ccef23649d2e54aea1b317be36b2dbde0f329 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 16 Jan 2023 15:44:46 +0100 Subject: gpio: merrifield: Use dev_err_probe() Improve error handling in the probe() function with dev_err_probe(). Signed-off-by: Andy Shevchenko --- drivers/gpio/gpio-merrifield.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c index 5c0b460fcd90..c64057343954 100644 --- a/drivers/gpio/gpio-merrifield.c +++ b/drivers/gpio/gpio-merrifield.c @@ -78,10 +78,8 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id return retval; retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev)); - if (retval) { - dev_err(&pdev->dev, "I/O memory mapping error\n"); - return retval; - } + if (retval) + return dev_err_probe(dev, retval, "I/O memory mapping error\n"); base = pcim_iomap_table(pdev)[1]; -- cgit v1.2.3 From dc537030647a451bca169209d05b50d2ca3fe4f6 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 16 Feb 2023 20:03:42 +0200 Subject: gpio: merrifield: Utilise temporary variable for struct device We have a temporary variable to keep pointer to struct device. Utilise it inside the ->probe() implementation. Signed-off-by: Andy Shevchenko --- drivers/gpio/gpio-merrifield.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c index c64057343954..421d7e3a6c66 100644 --- a/drivers/gpio/gpio-merrifield.c +++ b/drivers/gpio/gpio-merrifield.c @@ -51,12 +51,13 @@ static const struct tng_gpio_pinrange mrfld_gpio_ranges[] = { static const char *mrfld_gpio_get_pinctrl_dev_name(struct tng_gpio *priv) { + struct device *dev = priv->dev; struct acpi_device *adev; const char *name; adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1); if (adev) { - name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL); + name = devm_kstrdup(dev, acpi_dev_name(adev), GFP_KERNEL); acpi_dev_put(adev); } else { name = "pinctrl-merrifield"; @@ -89,11 +90,11 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id /* Release the IO mapping, since we already get the info from BAR1 */ pcim_iounmap_regions(pdev, BIT(1)); - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - priv->dev = &pdev->dev; + priv->dev = dev; priv->reg_base = pcim_iomap_table(pdev)[0]; priv->pin_info.pin_ranges = mrfld_gpio_ranges; -- cgit v1.2.3 From 9409d8cf78d9c5471cfd229e652f12050c6dbbde Mon Sep 17 00:00:00 2001 From: Pandith N Date: Thu, 16 Feb 2023 20:36:08 +0200 Subject: gpio: elkhartlake: Introduce Intel Elkhart Lake PSE GPIO This driver adds support for Intel Elkhart Lake PSE GPIO controller, using Intel Tangier as a library driver. Signed-off-by: Pandith N Co-developed-by: Raag Jadav Signed-off-by: Raag Jadav Co-developed-by: Andy Shevchenko Signed-off-by: Andy Shevchenko --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 12 ++++++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-elkhartlake.c | 90 +++++++++++++++++++++++++++++++++++++++++ drivers/gpio/gpio-tangier.h | 5 +++ 5 files changed, 109 insertions(+) create mode 100644 drivers/gpio/gpio-elkhartlake.c (limited to 'drivers/gpio') diff --git a/MAINTAINERS b/MAINTAINERS index 1176ae6b6d4c..958e5570cd59 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10281,6 +10281,7 @@ M: Andy Shevchenko L: linux-gpio@vger.kernel.org S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git +F: drivers/gpio/gpio-elkhartlake.c F: drivers/gpio/gpio-ich.c F: drivers/gpio/gpio-merrifield.c F: drivers/gpio/gpio-ml-ioh.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c769d29315e5..8f442ed4a322 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -625,6 +625,7 @@ config GPIO_TANGIER help GPIO support for Intel Tangier and compatible platforms. Currently supported: + - Elkhart Lake - Merrifield If built as a module its name will be gpio-tangier. @@ -1248,6 +1249,17 @@ config HTC_EGPIO several HTC phones. It provides basic support for input pins, output pins, and IRQs. +config GPIO_ELKHARTLAKE + tristate "Intel Elkhart Lake PSE GPIO support" + depends on X86 || COMPILE_TEST + select GPIO_TANGIER + help + Select this option to enable GPIO support for Intel Elkhart Lake + PSE GPIO IP. + + To compile this driver as a module, choose M here: the module will + be called gpio-elkhartlake. + config GPIO_JANZ_TTL tristate "Janz VMOD-TTL Digital IO Module" depends on MFD_JANZ_CMODIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d884abbf6156..594a443eba60 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o +obj-$(CONFIG_GPIO_ELKHARTLAKE) += gpio-elkhartlake.o obj-$(CONFIG_GPIO_EM) += gpio-em.o obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o diff --git a/drivers/gpio/gpio-elkhartlake.c b/drivers/gpio/gpio-elkhartlake.c new file mode 100644 index 000000000000..a9c8b16215be --- /dev/null +++ b/drivers/gpio/gpio-elkhartlake.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Elkhart Lake PSE GPIO driver + * + * Copyright (c) 2023 Intel Corporation. + * + * Authors: Pandith N + * Raag Jadav + */ + +#include +#include +#include +#include +#include + +#include "gpio-tangier.h" + +/* Each Intel EHL PSE GPIO Controller has 30 GPIO pins */ +#define EHL_PSE_NGPIO 30 + +static int ehl_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct tng_gpio *priv; + int irq, ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->reg_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->reg_base)) + return PTR_ERR(priv->reg_base); + + priv->dev = dev; + priv->irq = irq; + + priv->info.base = -1; + priv->info.ngpio = EHL_PSE_NGPIO; + + priv->wake_regs.gwmr = GWMR_EHL; + priv->wake_regs.gwsr = GWSR_EHL; + priv->wake_regs.gsir = GSIR_EHL; + + ret = devm_tng_gpio_probe(dev, priv); + if (ret) + return dev_err_probe(dev, ret, "tng_gpio_probe error\n"); + + platform_set_drvdata(pdev, priv); + return 0; +} + +static int ehl_gpio_suspend(struct device *dev) +{ + return tng_gpio_suspend(dev); +} + +static int ehl_gpio_resume(struct device *dev) +{ + return tng_gpio_resume(dev); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(ehl_gpio_pm_ops, ehl_gpio_suspend, ehl_gpio_resume); + +static const struct platform_device_id ehl_gpio_ids[] = { + { "gpio-elkhartlake" }, + { } +}; +MODULE_DEVICE_TABLE(platform, ehl_gpio_ids); + +static struct platform_driver ehl_gpio_driver = { + .driver = { + .name = "gpio-elkhartlake", + .pm = pm_sleep_ptr(&ehl_gpio_pm_ops), + }, + .probe = ehl_gpio_probe, + .id_table = ehl_gpio_ids, +}; +module_platform_driver(ehl_gpio_driver); + +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Raag Jadav "); +MODULE_DESCRIPTION("Intel Elkhart Lake PSE GPIO driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(GPIO_TANGIER); diff --git a/drivers/gpio/gpio-tangier.h b/drivers/gpio/gpio-tangier.h index 735b966db423..16c4f22908fb 100644 --- a/drivers/gpio/gpio-tangier.h +++ b/drivers/gpio/gpio-tangier.h @@ -20,6 +20,11 @@ struct device; struct tng_gpio_context; +/* Elkhart Lake specific wake registers */ +#define GWMR_EHL 0x100 /* Wake mask */ +#define GWSR_EHL 0x118 /* Wake source */ +#define GSIR_EHL 0x130 /* Secure input */ + /* Merrifield specific wake registers */ #define GWMR_MRFLD 0x400 /* Wake mask */ #define GWSR_MRFLD 0x418 /* Wake source */ -- cgit v1.2.3 From 56b16a9a80232fc70bebe31ded52c2f6fd3f7ddf Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 7 Mar 2023 10:54:27 -0600 Subject: gpio: ich: Use devm_gpiochip_add_data() to simplify remove path Use devm version of gpiochip add function to handle removal for us. Signed-off-by: Andrew Davis Signed-off-by: Andy Shevchenko --- drivers/gpio/gpio-ich.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c index 3b31f5e9bf40..0be9285efebc 100644 --- a/drivers/gpio/gpio-ich.c +++ b/drivers/gpio/gpio-ich.c @@ -457,7 +457,7 @@ static int ichx_gpio_probe(struct platform_device *pdev) init: ichx_gpiolib_setup(&ichx_priv.chip); - err = gpiochip_add_data(&ichx_priv.chip, NULL); + err = devm_gpiochip_add_data(dev, &ichx_priv.chip, NULL); if (err) { dev_err(dev, "Failed to register GPIOs\n"); return err; @@ -469,19 +469,11 @@ init: return 0; } -static int ichx_gpio_remove(struct platform_device *pdev) -{ - gpiochip_remove(&ichx_priv.chip); - - return 0; -} - static struct platform_driver ichx_gpio_driver = { .driver = { .name = DRV_NAME, }, .probe = ichx_gpio_probe, - .remove = ichx_gpio_remove, }; module_platform_driver(ichx_gpio_driver); -- cgit v1.2.3 From 2ffd04ca2ae66c274eb116d5f0330af14cb63383 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 14 Mar 2023 12:55:09 +0200 Subject: gpio: mm-lantiq: Fix typo in the newly added header filename The header with legacy struct of_mmio_gpio_chip and accompanying APIs is called legacy-of-mm-gpiochip.h. Remove repetitive '.h' at the end. Fixes: a99cc66807d6 ("gpiolib: split of_mm_gpio_chip out of linux/of_gpio.h") Reported-by: kernel test robot Signed-off-by: Andy Shevchenko --- drivers/gpio/gpio-mm-lantiq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpio-mm-lantiq.c b/drivers/gpio/gpio-mm-lantiq.c index 27ff84c5d162..f3c158259636 100644 --- a/drivers/gpio/gpio-mm-lantiq.c +++ b/drivers/gpio/gpio-mm-lantiq.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v1.2.3 From 5062e4c14b752a21aa24d6500ace6e251fde1d7c Mon Sep 17 00:00:00 2001 From: Benjamin Tissoires Date: Fri, 10 Mar 2023 14:38:10 +0100 Subject: gpiolib: acpi: use the fwnode in acpi_gpiochip_find() While trying to set up an SSDT override for a USB-2-I2C chip [0], I realized that the function acpi_gpiochip_find() was using the parent of the gpio_chip to do the ACPI matching. This works fine on my Ice Lake laptop because AFAICT, the DSDT presents the PCI device INT3455 as the "Device (GPI0)", but is in fact handled by the pinctrl driver in Linux. The pinctrl driver then creates a gpio_chip device. This means that the gc->parent device in that case is the GPI0 device from ACPI and everything works. However, in the hid-cp2112 case, the parent is the USB device, and the gpio_chip is directly under that USB device. Which means that in this case gc->parent points at the USB device, and so we can not do an ACPI match towards the GPIO device. I think it is safe to resolve the ACPI matching through the fwnode because when we call gpiochip_add_data(), the first thing it does is setting a proper gc->fwnode: if it is not there, it borrows the fwnode of the parent. So in my Ice Lake case, gc->fwnode is the one from the parent, meaning that the ACPI handle we will get is the one from the GPI0 in the DSDT (the pincrtl one). And in the hid-cp2112 case, we get the actual fwnode from the gpiochip we created in the HID device, making it working. Reviewed-by: Mika Westerberg Link: https://lore.kernel.org/linux-input/20230227140758.1575-1-kaehndan@gmail.com/T/#m592f18081ef3b95b618694a612ff864420c5aaf3 [0] Signed-off-by: Benjamin Tissoires Signed-off-by: Andy Shevchenko --- drivers/gpio/gpiolib-acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c index 0605399c84e7..47d34dbd7218 100644 --- a/drivers/gpio/gpiolib-acpi.c +++ b/drivers/gpio/gpiolib-acpi.c @@ -128,7 +128,7 @@ static bool acpi_gpio_deferred_req_irqs_done; static int acpi_gpiochip_find(struct gpio_chip *gc, void *data) { - return gc->parent && device_match_acpi_handle(gc->parent, data); + return ACPI_HANDLE_FWNODE(gc->fwnode) == data; } /** -- cgit v1.2.3 From af3b462a8e07bc5529e19f60d04a225bfce659e1 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 30 Jan 2023 18:13:45 +0200 Subject: gpiolib: acpi: Move ACPI device NULL check to acpi_get_driver_gpio_data() It's logical to check ACPI device for NULL inside acpi_get_driver_gpio_data() instead of requiring that in each caller. Signed-off-by: Andy Shevchenko --- drivers/gpio/gpiolib-acpi.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c index 47d34dbd7218..4d4a2a6172a2 100644 --- a/drivers/gpio/gpiolib-acpi.c +++ b/drivers/gpio/gpiolib-acpi.c @@ -645,7 +645,7 @@ static bool acpi_get_driver_gpio_data(struct acpi_device *adev, { const struct acpi_gpio_mapping *gm; - if (!adev->driver_gpios) + if (!adev || !adev->driver_gpios) return false; for (gm = adev->driver_gpios; gm->name; gm++) @@ -839,13 +839,10 @@ static int acpi_gpio_property_lookup(struct fwnode_handle *fwnode, ret = __acpi_node_get_property_reference(fwnode, propname, index, 3, &args); if (ret) { - struct acpi_device *adev = to_acpi_device_node(fwnode); + struct acpi_device *adev; - if (!adev) - return ret; - - if (!acpi_get_driver_gpio_data(adev, propname, index, &args, - &quirks)) + adev = to_acpi_device_node(fwnode); + if (!acpi_get_driver_gpio_data(adev, propname, index, &args, &quirks)) return ret; } /* -- cgit v1.2.3 From 782eea0c89f7d071d6b56ecfa1b8b0c81164b9be Mon Sep 17 00:00:00 2001 From: Werner Sembach Date: Wed, 22 Mar 2023 13:15:47 +0100 Subject: gpiolib: acpi: Add a ignore wakeup quirk for Clevo NL5xNU commit 1796f808e4bb ("HID: i2c-hid: acpi: Stop setting wakeup_capable") changed the policy such that I2C touchpads may be able to wake up the system by default if the system is configured as such. However on Clevo NL5xNU there is a mistake in the ACPI tables that the TP_ATTN# signal connected to GPIO 9 is configured as ActiveLow and level triggered but connected to a pull up. As soon as the system suspends the touchpad loses power and then the system wakes up. To avoid this problem, introduce a quirk for this model that will prevent the wakeup capability for being set for GPIO 9. This patch is analoge to a very similar patch for NL5xRU, just the DMI string changed. Signed-off-by: Werner Sembach Cc: stable@vger.kernel.org Signed-off-by: Andy Shevchenko --- drivers/gpio/gpiolib-acpi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c index 4d4a2a6172a2..b6321d827d91 100644 --- a/drivers/gpio/gpiolib-acpi.c +++ b/drivers/gpio/gpiolib-acpi.c @@ -1613,6 +1613,19 @@ static const struct dmi_system_id gpiolib_acpi_quirks[] __initconst = { .ignore_interrupt = "AMDI0030:00@18", }, }, + { + /* + * Spurious wakeups from TP_ATTN# pin + * Found in BIOS 1.7.8 + * https://gitlab.freedesktop.org/drm/amd/-/issues/1722#note_1720627 + */ + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "NL5xNU"), + }, + .driver_data = &(struct acpi_gpiolib_dmi_quirk) { + .ignore_wake = "ELAN0415:00@9", + }, + }, { /* * Spurious wakeups from TP_ATTN# pin -- cgit v1.2.3