From db7b0216c4e03bd4cf46edc1b85a7ae159f14703 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Thu, 21 May 2020 12:44:03 -0400 Subject: drm/amd/display: Add DCN3 HUBP Add support to program the DCN3 HUBP (Display to data fabric interface pipe) HW Blocks: +--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 41 +++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h') diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h index 8c04a3606a54..4a2c93087459 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h @@ -157,6 +157,12 @@ uint32_t VBLANK_PARAMETERS_5;\ uint32_t VBLANK_PARAMETERS_6 +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#define DCN30_HUBP_REG_COMMON_VARIABLE_LIST \ + DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ + uint32_t DCN_DMDATA_VM_CNTL +#endif + #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ DCN_HUBP_REG_FIELD_BASE_LIST(type); \ type DMDATA_ADDRESS_HIGH;\ @@ -192,17 +198,52 @@ type REFCYC_PER_META_CHUNK_FLIP_C; \ type VM_GROUP_SIZE +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \ + DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ + type PRIMARY_SURFACE_DCC_IND_BLK;\ + type SECONDARY_SURFACE_DCC_IND_BLK;\ + type PRIMARY_SURFACE_DCC_IND_BLK_C;\ + type SECONDARY_SURFACE_DCC_IND_BLK_C;\ + type ALPHA_PLANE_EN;\ + type REFCYC_PER_VM_DMDATA;\ + type DMDATA_VM_FAULT_STATUS;\ + type DMDATA_VM_FAULT_STATUS_CLEAR; \ + type DMDATA_VM_UNDERFLOW_STATUS;\ + type DMDATA_VM_LATE_STATUS;\ + type DMDATA_VM_UNDERFLOW_STATUS_CLEAR; \ + type DMDATA_VM_DONE; \ + type CROSSBAR_SRC_Y_G; \ + type CROSSBAR_SRC_ALPHA; \ + type PACK_3TO2_ELEMENT_DISABLE; \ + type ROW_TTU_MODE; \ + type NUM_PKRS +#endif struct dcn_hubp2_registers { +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCN30_HUBP_REG_COMMON_VARIABLE_LIST; +#else DCN21_HUBP_REG_COMMON_VARIABLE_LIST; +#endif }; struct dcn_hubp2_shift { +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); +#else DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); +#endif + }; struct dcn_hubp2_mask { +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); +#else DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); +#endif + }; struct dcn20_hubp { -- cgit v1.2.3