From 23eeae60b0fa9fb1af7623b42a55a719a4ec4597 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 25 Sep 2023 16:50:33 +0200 Subject: drm/msm/a6xx: Add missing regs for A7XX Add some missing definitions required for A7 support. This may be substituted with a mesa header sync. Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/559282/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/gpu/drm/msm/adreno/a6xx.xml.h') diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 1c051535fd4a..863b5e3b0e67 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1114,6 +1114,12 @@ enum a6xx_tex_type { #define REG_A6XX_CP_MISC_CNTL 0x00000840 #define REG_A6XX_CP_APRIV_CNTL 0x00000844 +#define A6XX_CP_APRIV_CNTL_CDWRITE 0x00000040 +#define A6XX_CP_APRIV_CNTL_CDREAD 0x00000020 +#define A6XX_CP_APRIV_CNTL_RBRPWB 0x00000008 +#define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL 0x00000004 +#define A6XX_CP_APRIV_CNTL_RBFETCH 0x00000002 +#define A6XX_CP_APRIV_CNTL_ICACHE 0x00000001 #define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0 @@ -1939,6 +1945,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f + #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 @@ -8252,5 +8260,6 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 +#define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039 #endif /* A6XX_XML */ -- cgit v1.2.3