From 89db07e5f71ef911fb6a32b5948f83f24666918e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 4 Sep 2023 05:04:51 +0300 Subject: drm/msm/dpu: enable INTF TE operations only when supported by HW The DPU_INTF_TE bit is set for all INTF blocks on DPU >= 5.0, however only INTF_1 and INTF_2 actually support tearing control (both are INTF_DSI). Rather than trying to limit the DPU_INTF_TE feature bit to those two INTF instances, check for the major && INTF type. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/555547/ Link: https://lore.kernel.org/r/20230904020454.2945667-6-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c') diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index bf7c6e1d3ea5..e8b8908d3e12 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -561,7 +561,10 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, if (cfg->features & BIT(DPU_INTF_INPUT_CTRL)) c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; - if (cfg->features & BIT(DPU_INTF_TE)) { + /* INTF TE is only for DSI interfaces */ + if (mdss_rev->core_major_ver >= 5 && cfg->type == INTF_DSI) { + WARN_ON(!cfg->intr_tear_rd_ptr); + c->ops.enable_tearcheck = dpu_hw_intf_enable_te; c->ops.disable_tearcheck = dpu_hw_intf_disable_te; c->ops.connect_external_te = dpu_hw_intf_connect_external_te; -- cgit v1.2.3