From 9e05fa1d24667fc2008e7f631aefd09acad80d77 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 24 Jan 2013 10:06:33 -0500 Subject: drm/radeon/cik: add hw cursor support (v2) CIK (DCE8) hw cursors are programmed the same as evergreen (DCE4) with the following caveats: - cursors are now 128x128 pixels - new alpha blend enable bit v2: rebase Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_display.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/radeon/radeon_display.c') diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index eb18bb7af1cc..1f850eb08c4f 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -153,7 +153,13 @@ static void dce5_crtc_load_lut(struct drm_crtc *crtc) NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); /* XXX match this to the depth of the crtc fmt block, move to modeset? */ WREG32(0x6940 + radeon_crtc->crtc_offset, 0); - + if (ASIC_IS_DCE8(rdev)) { + /* XXX this only needs to be programmed once per crtc at startup, + * not sure where the best place for it is + */ + WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, + CIK_CURSOR_ALPHA_BLND_ENA); + } } static void legacy_crtc_load_lut(struct drm_crtc *crtc) @@ -512,6 +518,14 @@ static void radeon_crtc_init(struct drm_device *dev, int index) radeon_crtc->crtc_id = index; rdev->mode_info.crtcs[index] = radeon_crtc; + if (rdev->family >= CHIP_BONAIRE) { + radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; + radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; + } else { + radeon_crtc->max_cursor_width = CURSOR_WIDTH; + radeon_crtc->max_cursor_height = CURSOR_HEIGHT; + } + #if 0 radeon_crtc->mode_set.crtc = &radeon_crtc->base; radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); -- cgit v1.2.3