From 7b829f6dd638c2cb45c7710bc7cd1d0395ea9bc1 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Thu, 27 Apr 2023 15:32:47 -0700 Subject: drm/xe/guc: Convert GuC registers to REG_FIELD/REG_BIT Cleanup GuC register declarations by converting them to use REG_FIELD, REG_BIT and REG_GENMASK. While converting, also reorder the bitfields so they follow the convention of declaring the higher bits first. v2: - Drop unused HUC_LOADING_AGENT_VCR and DMA_ADDRESS_SPACE_GTT (Matt Roper) - Simplify HUC_LOADING_AGENT_GUC define (Matt Roper) Reviewed-by: Matt Atwood Link: https://lore.kernel.org/r/20230427223256.1432787-2-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_ggtt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/xe/xe_ggtt.c') diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c index dbc45ef084b4..10a262a0c4cd 100644 --- a/drivers/gpu/drm/xe/xe_ggtt.c +++ b/drivers/gpu/drm/xe/xe_ggtt.c @@ -186,11 +186,11 @@ err: } #define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8) -#define GEN12_GUC_TLB_INV_CR_INVALIDATE (1 << 0) +#define GEN12_GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) #define PVC_GUC_TLB_INV_DESC0 _MMIO(0xcf7c) -#define PVC_GUC_TLB_INV_DESC0_VALID (1 << 0) +#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0) #define PVC_GUC_TLB_INV_DESC1 _MMIO(0xcf80) -#define PVC_GUC_TLB_INV_DESC1_INVALIDATE (1 << 6) +#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6) void xe_ggtt_invalidate(struct xe_gt *gt) { -- cgit v1.2.3