From eb8c88808c8307b05ce42e101753cb2518c6d14e Mon Sep 17 00:00:00 2001
From: Philipp Zabel
Date: Fri, 24 Feb 2017 18:31:05 +0100
Subject: drm/imx: add deferred plane disabling
The DP (display processor) channel disable code tried to busy wait for
the DP sync flow end interrupt status bit when disabling the partial
plane without a full modeset. That never worked reliably, and it was
disabled completely by the recent "gpu: ipu-v3: remove IRQ dance on DC
channel disable" patch, causing ipu_wait_interrupt to always time out
after 50 ms, which in turn would trigger a timeout in
drm_atomic_helper_wait_for_vblanks.
This patch changes ipu_plane_atomic_disable to only queue a DP channel
register update at the next frame boundary and set a flag, which can be
done without any waiting whatsoever. The imx_drm_atomic_commit_tail then
calls a new ipu_plane_disable_deferred function that does the actual
IDMAC teardown of the planes that are flagged for deferred disabling,
after waiting for the vblank.
Signed-off-by: Philipp Zabel
Reviewed-by: Lucas Stach
---
drivers/gpu/ipu-v3/ipu-dp.c | 3 ---
1 file changed, 3 deletions(-)
(limited to 'drivers/gpu/ipu-v3')
diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
index 0e09c98248a0..9b2b3fa479c4 100644
--- a/drivers/gpu/ipu-v3/ipu-dp.c
+++ b/drivers/gpu/ipu-v3/ipu-dp.c
@@ -277,9 +277,6 @@ void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync)
writel(0, flow->base + DP_FG_POS);
ipu_srm_dp_update(priv->ipu, sync);
- if (ipu_idmac_channel_busy(priv->ipu, IPUV3_CHANNEL_MEM_BG_SYNC))
- ipu_wait_interrupt(priv->ipu, IPU_IRQ_DP_SF_END, 50);
-
mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dp_disable_channel);
--
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