From ff11f5bc5a42f2cfc9705481eedf1b4d470ade2c Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Wed, 2 Aug 2017 10:22:13 -0600 Subject: coresight tmc etr: Detect address width at runtime TMC in Coresight SoC-600 advertises the AXI address width in the device configuration register. Bit 16 - AXIAW_VALID 0 - AXI Address Width not valid 1 - Valid AXI Address width in Bits[23-17] Bits [23-17] - AXIAW. If AXIAW_VALID = b01 then 0x20 - 32bit AXI address bus 0x28 - 40bit AXI address bus 0x2c - 44bit AXI address bus 0x30 - 48bit AXI address bus 0x34 - 52bit AXI address bus Use the address bits from the device configuration register, if available. Otherwise, default to 40bit. Cc: Mathieu Poirier Cc: Robin Murphy Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/coresight/coresight-tmc.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/hwtracing/coresight/coresight-tmc.h') diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index bb6a3e3314b8..f55203d48673 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -71,6 +71,10 @@ #define TMC_DEVID_NOSCAT BIT(24) +#define TMC_DEVID_AXIAW_VALID BIT(16) +#define TMC_DEVID_AXIAW_SHIFT 17 +#define TMC_DEVID_AXIAW_MASK 0x7f + enum tmc_config_type { TMC_CONFIG_TYPE_ETB, TMC_CONFIG_TYPE_ETR, -- cgit v1.2.3