From ac0ba2100298a3e85d9a92924a959b80612144e6 Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Tue, 25 Jan 2022 19:50:35 +0530 Subject: coresight: trbe: Work around the ignored system register writes TRBE implementations affected by Arm erratum #2064142 might fail to write into certain system registers after the TRBE has been disabled. Under some conditions after TRBE has been disabled, writes into certain TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1 and TRBTRG_EL1 will be ignored and not be effected. Work around this problem in the TRBE driver by executing TSB CSYNC and DSB just after the trace collection has stopped and before performing a system register write to one of the affected registers. This just updates the TRBE driver as required. Cc: Catalin Marinas Cc: Will Deacon Cc: Mathieu Poirier Cc: Suzuki Poulose Cc: coresight@lists.linaro.org Cc: linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Suzuki K Poulose Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/1643120437-14352-6-git-send-email-anshuman.khandual@arm.com Signed-off-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-trbe.c | 54 +++++++++++++++++++--------- drivers/hwtracing/coresight/coresight-trbe.h | 8 ----- 2 files changed, 38 insertions(+), 24 deletions(-) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 276862c07e32..4ef944971d8e 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -91,10 +91,12 @@ struct trbe_buf { */ #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 +#define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 static int trbe_errata_cpucaps[] = { [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, + [TRBE_NEEDS_DRAIN_AFTER_DISABLE] = ARM64_WORKAROUND_2064142, -1, /* Sentinel, must be the last entry */ }; @@ -167,6 +169,16 @@ static inline bool trbe_may_write_out_of_range(struct trbe_cpudata *cpudata) return trbe_has_erratum(cpudata, TRBE_WORKAROUND_WRITE_OUT_OF_RANGE); } +static inline bool trbe_needs_drain_after_disable(struct trbe_cpudata *cpudata) +{ + /* + * Errata affected TRBE implementation will need TSB CSYNC and + * DSB in order to prevent subsequent writes into certain TRBE + * system registers from being ignored and not effected. + */ + return trbe_has_erratum(cpudata, TRBE_NEEDS_DRAIN_AFTER_DISABLE); +} + static int trbe_alloc_node(struct perf_event *event) { if (event->cpu == -1) @@ -174,30 +186,37 @@ static int trbe_alloc_node(struct perf_event *event) return cpu_to_node(event->cpu); } -static void trbe_drain_buffer(void) +static inline void trbe_drain_buffer(void) { tsb_csync(); dsb(nsh); } -static void trbe_drain_and_disable_local(void) +static inline void set_trbe_disabled(struct trbe_cpudata *cpudata) { u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); - trbe_drain_buffer(); - /* * Disable the TRBE without clearing LIMITPTR which * might be required for fetching the buffer limits. */ trblimitr &= ~TRBLIMITR_ENABLE; write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); + + if (trbe_needs_drain_after_disable(cpudata)) + trbe_drain_buffer(); isb(); } -static void trbe_reset_local(void) +static void trbe_drain_and_disable_local(struct trbe_cpudata *cpudata) { - trbe_drain_and_disable_local(); + trbe_drain_buffer(); + set_trbe_disabled(cpudata); +} + +static void trbe_reset_local(struct trbe_cpudata *cpudata) +{ + trbe_drain_and_disable_local(cpudata); write_sysreg_s(0, SYS_TRBLIMITR_EL1); write_sysreg_s(0, SYS_TRBPTR_EL1); write_sysreg_s(0, SYS_TRBBASER_EL1); @@ -234,7 +253,7 @@ static void trbe_stop_and_truncate_event(struct perf_output_handle *handle) * at event_stop(). So disable the TRBE here and leave * the update_buffer() to return a 0 size. */ - trbe_drain_and_disable_local(); + trbe_drain_and_disable_local(buf->cpudata); perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); perf_aux_output_end(handle, 0); *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL; @@ -579,8 +598,7 @@ static void trbe_enable_hw(struct trbe_buf *buf) WARN_ON(buf->trbe_hw_base < buf->trbe_base); WARN_ON(buf->trbe_write < buf->trbe_hw_base); WARN_ON(buf->trbe_write >= buf->trbe_limit); - set_trbe_disabled(); - isb(); + set_trbe_disabled(buf->cpudata); clr_trbe_status(); set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); @@ -775,7 +793,7 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev, * the TRBE here will ensure that no IRQ could be generated when the perf * handle gets freed in etm_event_stop(). */ - trbe_drain_and_disable_local(); + trbe_drain_and_disable_local(cpudata); /* Check if there is a pending interrupt and handle it here */ status = read_sysreg_s(SYS_TRBSR_EL1); @@ -986,7 +1004,7 @@ static int arm_trbe_disable(struct coresight_device *csdev) if (cpudata->mode != CS_MODE_PERF) return -EINVAL; - trbe_drain_and_disable_local(); + trbe_drain_and_disable_local(cpudata); buf->cpudata = NULL; cpudata->buf = NULL; cpudata->mode = CS_MODE_DISABLED; @@ -1028,7 +1046,7 @@ static int trbe_handle_overflow(struct perf_output_handle *handle) * is able to detect this with a disconnected handle * (handle->event = NULL). */ - trbe_drain_and_disable_local(); + trbe_drain_and_disable_local(buf->cpudata); *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL; return -EINVAL; } @@ -1062,6 +1080,7 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev) { struct perf_output_handle **handle_ptr = dev; struct perf_output_handle *handle = *handle_ptr; + struct trbe_buf *buf = etm_perf_sink_config(handle); enum trbe_fault_action act; u64 status; bool truncated = false; @@ -1082,7 +1101,7 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev) * Ensure the trace is visible to the CPUs and * any external aborts have been resolved. */ - trbe_drain_and_disable_local(); + trbe_drain_and_disable_local(buf->cpudata); clr_trbe_irq(); isb(); @@ -1167,8 +1186,9 @@ static const struct attribute_group *arm_trbe_groups[] = { static void arm_trbe_enable_cpu(void *info) { struct trbe_drvdata *drvdata = info; + struct trbe_cpudata *cpudata = this_cpu_ptr(drvdata->cpudata); - trbe_reset_local(); + trbe_reset_local(cpudata); enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE); } @@ -1276,7 +1296,7 @@ static void arm_trbe_remove_coresight_cpu(void *info) struct coresight_device *trbe_csdev = coresight_get_percpu_sink(cpu); disable_percpu_irq(drvdata->irq); - trbe_reset_local(); + trbe_reset_local(cpudata); if (trbe_csdev) { coresight_unregister(trbe_csdev); cpudata->drvdata = NULL; @@ -1349,8 +1369,10 @@ static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node) struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node); if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) { + struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); + disable_percpu_irq(drvdata->irq); - trbe_reset_local(); + trbe_reset_local(cpudata); } return 0; } diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h index abf3e36082f0..30e4d7db4f8e 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -91,14 +91,6 @@ static inline bool is_trbe_running(u64 trbsr) #define TRBE_FILL_MODE_WRAP 1 #define TRBE_FILL_MODE_CIRCULAR_BUFFER 3 -static inline void set_trbe_disabled(void) -{ - u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); - - trblimitr &= ~TRBLIMITR_ENABLE; - write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); -} - static inline bool get_trbe_flag_update(u64 trbidr) { return trbidr & TRBIDR_FLAG; -- cgit v1.2.3 From f209e9fe5bd7614b30b050f2095e80b77b99c333 Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Tue, 25 Jan 2022 19:50:36 +0530 Subject: coresight: trbe: Work around the invalid prohibited states TRBE implementations affected by Arm erratum #2038923 might get TRBE into an inconsistent view on whether trace is prohibited within the CPU. As a result, the trace buffer or trace buffer state might be corrupted. This happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, followed by just a single context synchronization event before execution changes from a context, in which trace is prohibited to one where it isn't, or vice versa. In these mentioned conditions, the view of whether trace is prohibited is inconsistent between parts of the CPU, and the trace buffer or the trace buffer state might be corrupted. Work around this problem in the TRBE driver by preventing an inconsistent view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or two ISB instructions if no ERET is to take place. This just updates the TRBE driver as required. Cc: Catalin Marinas Cc: Will Deacon Cc: Mathieu Poirier Cc: Suzuki Poulose Cc: coresight@lists.linaro.org Cc: linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Suzuki K Poulose Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/1643120437-14352-7-git-send-email-anshuman.khandual@arm.com Signed-off-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- arch/arm64/Kconfig | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 48 +++++++++++++++++++++------- 2 files changed, 37 insertions(+), 13 deletions(-) (limited to 'drivers/hwtracing') diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 93980bf31e2c..8c7df3405de2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -824,7 +824,7 @@ config ARM64_ERRATUM_2064142 config ARM64_ERRATUM_2038923 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in + depends on CORESIGHT_TRBE default y help This option adds the workaround for ARM Cortex-A510 erratum 2038923. diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 4ef944971d8e..6254ba598df2 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -92,11 +92,13 @@ struct trbe_buf { #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 #define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 +#define TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE 3 static int trbe_errata_cpucaps[] = { [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, [TRBE_NEEDS_DRAIN_AFTER_DISABLE] = ARM64_WORKAROUND_2064142, + [TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE] = ARM64_WORKAROUND_2038923, -1, /* Sentinel, must be the last entry */ }; @@ -179,6 +181,17 @@ static inline bool trbe_needs_drain_after_disable(struct trbe_cpudata *cpudata) return trbe_has_erratum(cpudata, TRBE_NEEDS_DRAIN_AFTER_DISABLE); } +static inline bool trbe_needs_ctxt_sync_after_enable(struct trbe_cpudata *cpudata) +{ + /* + * Errata affected TRBE implementation will need an additional + * context synchronization in order to prevent an inconsistent + * TRBE prohibited region view on the CPU which could possibly + * corrupt the TRBE buffer or the TRBE state. + */ + return trbe_has_erratum(cpudata, TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE); +} + static int trbe_alloc_node(struct perf_event *event) { if (event->cpu == -1) @@ -192,6 +205,22 @@ static inline void trbe_drain_buffer(void) dsb(nsh); } +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata, u64 trblimitr) +{ + /* + * Enable the TRBE without clearing LIMITPTR which + * might be required for fetching the buffer limits. + */ + trblimitr |= TRBLIMITR_ENABLE; + write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); + + /* Synchronize the TRBE enable event */ + isb(); + + if (trbe_needs_ctxt_sync_after_enable(cpudata)) + isb(); +} + static inline void set_trbe_disabled(struct trbe_cpudata *cpudata) { u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); @@ -555,9 +584,10 @@ static void clr_trbe_status(void) write_sysreg_s(trbsr, SYS_TRBSR_EL1); } -static void set_trbe_limit_pointer_enabled(unsigned long addr) +static void set_trbe_limit_pointer_enabled(struct trbe_buf *buf) { u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); + unsigned long addr = buf->trbe_limit; WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT))); WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); @@ -585,12 +615,7 @@ static void set_trbe_limit_pointer_enabled(unsigned long addr) trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT; trblimitr |= (addr & PAGE_MASK); - - trblimitr |= TRBLIMITR_ENABLE; - write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); - - /* Synchronize the TRBE enable event */ - isb(); + set_trbe_enabled(buf->cpudata, trblimitr); } static void trbe_enable_hw(struct trbe_buf *buf) @@ -608,7 +633,7 @@ static void trbe_enable_hw(struct trbe_buf *buf) * till now before enabling the TRBE. */ isb(); - set_trbe_limit_pointer_enabled(buf->trbe_limit); + set_trbe_limit_pointer_enabled(buf); } static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle, @@ -1013,16 +1038,15 @@ static int arm_trbe_disable(struct coresight_device *csdev) static void trbe_handle_spurious(struct perf_output_handle *handle) { - u64 limitr = read_sysreg_s(SYS_TRBLIMITR_EL1); + struct trbe_buf *buf = etm_perf_sink_config(handle); + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); /* * If the IRQ was spurious, simply re-enable the TRBE * back without modifying the buffer parameters to * retain the trace collected so far. */ - limitr |= TRBLIMITR_ENABLE; - write_sysreg_s(limitr, SYS_TRBLIMITR_EL1); - isb(); + set_trbe_enabled(buf->cpudata, trblimitr); } static int trbe_handle_overflow(struct perf_output_handle *handle) -- cgit v1.2.3 From 3a828845ae35626c2c8de4c46f5c602c25bd122d Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Tue, 25 Jan 2022 19:50:37 +0530 Subject: coresight: trbe: Work around the trace data corruption TRBE implementations affected by Arm erratum #1902691 might corrupt trace data or deadlock, when it's being written into the memory. Workaround this problem in the driver, by preventing TRBE initialization on affected cpus. The firmware must have disabled the access to TRBE for the kernel on such implementations. This will cover the kernel for any firmware that doesn't do this already. This just updates the TRBE driver as required. Cc: Catalin Marinas Cc: Will Deacon Cc: Mathieu Poirier Cc: Suzuki Poulose Cc: coresight@lists.linaro.org Cc: linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Suzuki K Poulose Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/1643120437-14352-8-git-send-email-anshuman.khandual@arm.com Signed-off-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- arch/arm64/Kconfig | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'drivers/hwtracing') diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 8c7df3405de2..390f0b1d0144 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -847,7 +847,7 @@ config ARM64_ERRATUM_2038923 config ARM64_ERRATUM_1902691 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in + depends on CORESIGHT_TRBE default y help This option adds the workaround for ARM Cortex-A510 erratum 1902691. diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 6254ba598df2..75b608bc400b 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -93,12 +93,14 @@ struct trbe_buf { #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 #define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 #define TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE 3 +#define TRBE_IS_BROKEN 4 static int trbe_errata_cpucaps[] = { [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, [TRBE_NEEDS_DRAIN_AFTER_DISABLE] = ARM64_WORKAROUND_2064142, [TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE] = ARM64_WORKAROUND_2038923, + [TRBE_IS_BROKEN] = ARM64_WORKAROUND_1902691, -1, /* Sentinel, must be the last entry */ }; @@ -192,6 +194,11 @@ static inline bool trbe_needs_ctxt_sync_after_enable(struct trbe_cpudata *cpudat return trbe_has_erratum(cpudata, TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE); } +static inline bool trbe_is_broken(struct trbe_cpudata *cpudata) +{ + return trbe_has_erratum(cpudata, TRBE_IS_BROKEN); +} + static int trbe_alloc_node(struct perf_event *event) { if (event->cpu == -1) @@ -1288,6 +1295,11 @@ static void arm_trbe_probe_cpu(void *info) */ trbe_check_errata(cpudata); + if (trbe_is_broken(cpudata)) { + pr_err("Disabling TRBE on cpu%d due to erratum\n", cpu); + goto cpu_clear; + } + /* * If the TRBE is affected by erratum TRBE_WORKAROUND_OVERWRITE_FILL_MODE, * we must always program the TBRPTR_EL1, 256bytes from a page -- cgit v1.2.3 From ea75a342aed5ed72c87f38fbe0df2f5df7eae374 Mon Sep 17 00:00:00 2001 From: James Clark Date: Thu, 20 Jan 2022 11:30:47 +0000 Subject: coresight: Fix TRCCONFIGR.QE sysfs interface It's impossible to program a valid value for TRCCONFIGR.QE when TRCIDR0.QSUPP==0b10. In that case the following is true: Q element support is implemented, and only supports Q elements without instruction counts. TRCCONFIGR.QE can only take the values 0b00 or 0b11. Currently the low bit of QSUPP is checked to see if the low bit of QE can be written to, but as you can see when QSUPP==0b10 the low bit is cleared making it impossible to ever write the only valid value of 0b11 to QE. 0b10 would be written instead, which is a reserved QE value even for all values of QSUPP. The fix is to allow writing the low bit of QE for any non zero value of QSUPP. This change also ensures that the low bit is always set, even when the user attempts to only set the high bit. Signed-off-by: James Clark Reviewed-by: Mike Leach Fixes: d8c66962084f ("coresight-etm4x: Controls pertaining to the reset, mode, pe and events") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220120113047.2839622-2-james.clark@arm.com Signed-off-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index a0640fa5c55b..57e94424a8d6 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -367,8 +367,12 @@ static ssize_t mode_store(struct device *dev, mode = ETM_MODE_QELEM(config->mode); /* start by clearing QE bits */ config->cfg &= ~(BIT(13) | BIT(14)); - /* if supported, Q elements with instruction counts are enabled */ - if ((mode & BIT(0)) && (drvdata->q_support & BIT(0))) + /* + * if supported, Q elements with instruction counts are enabled. + * Always set the low bit for any requested mode. Valid combos are + * 0b00, 0b01 and 0b11. + */ + if (mode && drvdata->q_support) config->cfg |= BIT(13); /* * if supported, Q elements with and without instruction -- cgit v1.2.3 From cfa5dbcdd7aece76f3415284569f2f384aff0253 Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Mon, 24 Jan 2022 12:41:21 +0000 Subject: coresight: syscfg: Fix memleak on registration failure in cscfg_create_device device_register() calls device_initialize(), according to doc of device_initialize: Use put_device() to give up your reference instead of freeing * @dev directly once you have called this function. To prevent potential memleak, use put_device() for error handling. Signed-off-by: Miaoqian Lin Fixes: 85e2414c518a ("coresight: syscfg: Initial coresight system configuration") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220124124121.8888-1-linmq006@gmail.com Signed-off-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-syscfg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index 098fc34c4829..11850fd8c3b5 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -1049,7 +1049,7 @@ static int cscfg_create_device(void) err = device_register(dev); if (err) - cscfg_dev_release(dev); + put_device(dev); create_dev_exit_unlock: mutex_unlock(&cscfg_mutex); -- cgit v1.2.3 From 27caf7e473ef4b9d94a4a7d00e27ce6b24ad1b28 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Tue, 1 Feb 2022 18:58:09 +0100 Subject: hwtracing: coresight: Replace acpi_bus_get_device() Replace acpi_bus_get_device() that is going to be dropped with acpi_fetch_acpi_dev(). No intentional functional impact. Signed-off-by: Rafael J. Wysocki Link: https://lore.kernel.org/r/5790600.lOV4Wx5bFT@kreacher Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-platform.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c index c594f45319fc..475899714104 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -626,7 +626,7 @@ static int acpi_coresight_parse_link(struct acpi_device *adev, const union acpi_object *link, struct coresight_connection *conn) { - int rc, dir; + int dir; const union acpi_object *fields; struct acpi_device *r_adev; struct device *rdev; @@ -643,9 +643,9 @@ static int acpi_coresight_parse_link(struct acpi_device *adev, fields[3].type != ACPI_TYPE_INTEGER) return -EINVAL; - rc = acpi_bus_get_device(fields[2].reference.handle, &r_adev); - if (rc) - return rc; + r_adev = acpi_fetch_acpi_dev(fields[2].reference.handle); + if (!r_adev) + return -ENODEV; dir = fields[3].integer.value; if (dir == ACPI_CORESIGHT_LINK_MASTER) { -- cgit v1.2.3 From d05bbad0130ff86b802e5cd6acbb6cac23b841b8 Mon Sep 17 00:00:00 2001 From: James Clark Date: Thu, 3 Feb 2022 11:53:35 +0000 Subject: coresight: no-op refactor to make INSTP0 check more idiomatic The spec says this: P0 tracing support field. The permitted values are: 0b00 Tracing of load and store instructions as P0 elements is not supported. 0b11 Tracing of load and store instructions as P0 elements is supported, so TRCCONFIGR.INSTP0 is supported. All other values are reserved. The value we are looking for is 0b11 so simplify this. The double read and && was a bit obfuscated. Suggested-by: Suzuki Poulose Signed-off-by: James Clark Link: https://lore.kernel.org/r/20220203115336.119735-2-james.clark@arm.com Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index bf18128cf5de..e2eebd865241 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1091,7 +1091,7 @@ static void etm4_init_arch_data(void *info) etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); /* INSTP0, bits[2:1] P0 tracing support field */ - if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) + if (BMVAL(etmidr0, 1, 2) == 0b11) drvdata->instrp0 = true; else drvdata->instrp0 = false; -- cgit v1.2.3 From ef1dacf4b3e23dae57d741bb592a3393428c5a7d Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Thu, 3 Feb 2022 19:01:59 +0000 Subject: coresight: trbe: Move check for kernel page table isolation from EL0 to probe Currently with the check present in the module initialisation, it shouts on all the systems irrespective of presence of coresight trace buffer extensions. Similar to Arm SPE perf driver, move the check for kernel page table isolation from EL0 to the device probe stage instead of the module initialisation so that it complains only on the systems that support TRBE. Cc: Mathieu Poirier Cc: Suzuki K Poulose Cc: Mike Leach Cc: Leo Yan Cc: Anshuman Khandual Cc: coresight@lists.linaro.org Signed-off-by: Sudeep Holla Reviewed-by: Anshuman Khandual Link: https://lore.kernel.org/r/20220203190159.3145272-1-sudeep.holla@arm.com Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-trbe.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 75b608bc400b..2b386bb848f8 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1481,6 +1481,12 @@ static int arm_trbe_device_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; int ret; + /* Trace capture is not possible with kernel page table isolation */ + if (arm64_kernel_unmapped_at_el0()) { + pr_err("TRBE wouldn't work if kernel gets unmapped at EL0\n"); + return -EOPNOTSUPP; + } + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; @@ -1542,11 +1548,6 @@ static int __init arm_trbe_init(void) { int ret; - if (arm64_kernel_unmapped_at_el0()) { - pr_err("TRBE wouldn't work if kernel gets unmapped at EL0\n"); - return -EOPNOTSUPP; - } - ret = platform_driver_register(&arm_trbe_driver); if (!ret) return 0; -- cgit v1.2.3 From bf0ef4f12c6303879c04e05ce43ea37ac56ebfa6 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Fri, 4 Feb 2022 23:24:00 +0800 Subject: coresight: etm4x: Add lock for reading virtual context ID comparator Updates to the values and the index are protected via the spinlock. Ensure we use the same lock to read the value safely. Signed-off-by: Leo Yan Reviewed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20220204152403.71775-2-leo.yan@linaro.org --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 57e94424a8d6..c376f9e230d3 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2115,7 +2115,9 @@ static ssize_t vmid_val_show(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + spin_lock(&drvdata->spinlock); val = (unsigned long)config->vmid_val[config->vmid_idx]; + spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } -- cgit v1.2.3 From 1314dd1971309a84b594cfb6269260e9e9c2c31a Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Fri, 4 Feb 2022 23:24:01 +0800 Subject: coresight: etm4x: Don't use virtual contextID for non-root PID namespace As commented in the function ctxid_pid_store(), it can cause the PID values mismatching between context ID tracing and PID allocated in a non-root namespace. For this reason, when a process runs in non-root PID namespace, the driver doesn't allow PID tracing and returns failure when access contextID related sysfs nodes. VMID works for virtual contextID when the kernel runs in EL2 mode with VHE; on the other hand, the driver doesn't prevent users from accessing it when programs run in the non-root namespace. Thus this can lead to same issues with contextID described above. This patch imposes the checking on VMID related sysfs knobs and returns failure if current process runs in non-root PID namespace. Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20220204152403.71775-3-leo.yan@linaro.org --- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index c376f9e230d3..21687cc1e4e2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2115,6 +2115,13 @@ static ssize_t vmid_val_show(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + /* + * Don't use virtual contextID tracing if coming from a PID namespace. + * See comment in ctxid_pid_store(). + */ + if (!task_is_in_init_pid_ns(current)) + return -EINVAL; + spin_lock(&drvdata->spinlock); val = (unsigned long)config->vmid_val[config->vmid_idx]; spin_unlock(&drvdata->spinlock); @@ -2129,6 +2136,13 @@ static ssize_t vmid_val_store(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + /* + * Don't use virtual contextID tracing if coming from a PID namespace. + * See comment in ctxid_pid_store(). + */ + if (!task_is_in_init_pid_ns(current)) + return -EINVAL; + /* * only implemented when vmid tracing is enabled, i.e. at least one * vmid comparator is implemented and at least 8 bit vmid size @@ -2152,6 +2166,13 @@ static ssize_t vmid_masks_show(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + /* + * Don't use virtual contextID tracing if coming from a PID namespace. + * See comment in ctxid_pid_store(). + */ + if (!task_is_in_init_pid_ns(current)) + return -EINVAL; + spin_lock(&drvdata->spinlock); val1 = config->vmid_mask0; val2 = config->vmid_mask1; @@ -2169,6 +2190,13 @@ static ssize_t vmid_masks_store(struct device *dev, struct etmv4_config *config = &drvdata->config; int nr_inputs; + /* + * Don't use virtual contextID tracing if coming from a PID namespace. + * See comment in ctxid_pid_store(). + */ + if (!task_is_in_init_pid_ns(current)) + return -EINVAL; + /* * only implemented when vmid tracing is enabled, i.e. at least one * vmid comparator is implemented and at least 8 bit vmid size -- cgit v1.2.3 From aab473867fed4a0b29f9456286d8f680be0ab314 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Fri, 4 Feb 2022 23:24:02 +0800 Subject: coresight: etm4x: Don't trace PID for non-root PID namespace When runs in perf mode, the driver always enables the PID tracing. This can lead confusion when the profiling session runs in non-root PID namespace, whereas it records the PIDs from the root PID namespace. To avoid confusion for PID tracing, when runs in perf mode, this patch changes to only enable PID tracing for root PID namespace. As result, after apply this patch, the perf tool reports PID as '-1' for all samples: # unshare --fork --pid perf record -e cs_etm// -m 64K,64K -a \ -o perf_test.data -- uname # perf report -i perf_test.data --itrace=Zi1000i --stdio # Total Lost Samples: 0 # # Samples: 94 of event 'instructions' # Event count (approx.): 94000 # # Overhead Command Shared Object Symbol # ........ ....... ................. .............................. # 68.09% :-1 [kernel.kallsyms] [k] __sched_text_end 3.19% :-1 [kernel.kallsyms] [k] hrtimer_interrupt 2.13% :-1 [kernel.kallsyms] [k] __bitmap_and 2.13% :-1 [kernel.kallsyms] [k] trace_vbprintk 1.06% :-1 [kernel.kallsyms] [k] __fget_files 1.06% :-1 [kernel.kallsyms] [k] __schedule 1.06% :-1 [kernel.kallsyms] [k] __softirqentry_text_start 1.06% :-1 [kernel.kallsyms] [k] __update_load_avg_cfs_rq 1.06% :-1 [kernel.kallsyms] [k] __update_load_avg_se 1.06% :-1 [kernel.kallsyms] [k] arch_counter_get_cntpct 1.06% :-1 [kernel.kallsyms] [k] check_and_switch_context 1.06% :-1 [kernel.kallsyms] [k] format_decode 1.06% :-1 [kernel.kallsyms] [k] handle_percpu_devid_irq 1.06% :-1 [kernel.kallsyms] [k] irq_enter_rcu 1.06% :-1 [kernel.kallsyms] [k] irqtime_account_irq 1.06% :-1 [kernel.kallsyms] [k] ktime_get 1.06% :-1 [kernel.kallsyms] [k] ktime_get_coarse_real_ts64 1.06% :-1 [kernel.kallsyms] [k] memmove 1.06% :-1 [kernel.kallsyms] [k] perf_ioctl 1.06% :-1 [kernel.kallsyms] [k] perf_output_begin 1.06% :-1 [kernel.kallsyms] [k] perf_output_copy 1.06% :-1 [kernel.kallsyms] [k] profile_tick 1.06% :-1 [kernel.kallsyms] [k] sched_clock 1.06% :-1 [kernel.kallsyms] [k] timerqueue_add 1.06% :-1 [kernel.kallsyms] [k] trace_save_cmdline 1.06% :-1 [kernel.kallsyms] [k] update_load_avg 1.06% :-1 [kernel.kallsyms] [k] vbin_printf Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20220204152403.71775-4-leo.yan@linaro.org --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index e2eebd865241..7f416a12000e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -656,7 +656,9 @@ static int etm4_parse_event_config(struct coresight_device *csdev, config->cfg |= BIT(11); } - if (attr->config & BIT(ETM_OPT_CTXTID)) + /* Only trace contextID when runs in root PID namespace */ + if ((attr->config & BIT(ETM_OPT_CTXTID)) && + task_is_in_init_pid_ns(current)) /* bit[6], Context ID tracing bit */ config->cfg |= BIT(ETM4_CFG_BIT_CTXTID); @@ -670,7 +672,11 @@ static int etm4_parse_event_config(struct coresight_device *csdev, ret = -EINVAL; goto out; } - config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT); + + /* Only trace virtual contextID when runs in root PID namespace */ + if (task_is_in_init_pid_ns(current)) + config->cfg |= BIT(ETM4_CFG_BIT_VMID) | + BIT(ETM4_CFG_BIT_VMID_OPT); } /* return stack - enable if selected and supported */ -- cgit v1.2.3 From ec70b05d5da9ac753868e55607298b0699a7ad27 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Fri, 4 Feb 2022 23:24:03 +0800 Subject: coresight: etm3x: Don't trace PID for non-root PID namespace ETMv3 driver enables PID tracing by directly using perf config from userspace, this means the tracer will capture PID packets from root namespace but the profiling session runs in non-root PID namespace. Finally, the recorded packets can mislead perf reporting with the mismatched PID values. This patch changes to only enable PID tracing for root PID namespace. Note, the hardware supports VMID tracing from ETMv3.5, but the driver never enables VMID trace, this patch doesn't handle VMID trace (bit 30 in ETMCR register) particularly. Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20220204152403.71775-5-leo.yan@linaro.org --- drivers/hwtracing/coresight/coresight-etm3x-core.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index cf64ce73a741..7d413ba8b823 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -340,6 +340,10 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, config->ctrl = attr->config; + /* Don't trace contextID when runs in non-root PID namespace */ + if (!task_is_in_init_pid_ns(current)) + config->ctrl &= ~ETMCR_CTXID_SIZE; + /* * Possible to have cores with PTM (supports ret stack) and ETM * (never has ret stack) on the same SoC. So if we have a request -- cgit v1.2.3 From 286f950545e0d9c8aa802cbfc9676860bbc49179 Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Wed, 16 Feb 2022 15:21:58 +0530 Subject: coresight: Drop unused 'none' enum value for each component CORESIGHT_DEV_TYPE_NONE/CORESIGHT_DEV_SUBTYPE_XXXX_NONE values are not used any where. Actual enumeration can start from 0. Just drop these unused enum values. Cc: Mathieu Poirier Cc: Suzuki K Poulose Cc: Mike Leach Cc: Leo Yan Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/1645005118-10561-1-git-send-email-anshuman.khandual@arm.com Signed-off-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-core.c | 3 --- include/linux/coresight.h | 5 ----- 2 files changed, 8 deletions(-) (limited to 'drivers/hwtracing') diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 88653d1c06a4..af00dca8d1ac 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1278,9 +1278,6 @@ static struct attribute *coresight_source_attrs[] = { ATTRIBUTE_GROUPS(coresight_source); static struct device_type coresight_dev_type[] = { - { - .name = "none", - }, { .name = "sink", .groups = coresight_sink_groups, diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 93a2922b7653..9f445f09fcfe 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -36,7 +36,6 @@ extern struct bus_type coresight_bustype; enum coresight_dev_type { - CORESIGHT_DEV_TYPE_NONE, CORESIGHT_DEV_TYPE_SINK, CORESIGHT_DEV_TYPE_LINK, CORESIGHT_DEV_TYPE_LINKSINK, @@ -46,7 +45,6 @@ enum coresight_dev_type { }; enum coresight_dev_subtype_sink { - CORESIGHT_DEV_SUBTYPE_SINK_NONE, CORESIGHT_DEV_SUBTYPE_SINK_PORT, CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, @@ -54,21 +52,18 @@ enum coresight_dev_subtype_sink { }; enum coresight_dev_subtype_link { - CORESIGHT_DEV_SUBTYPE_LINK_NONE, CORESIGHT_DEV_SUBTYPE_LINK_MERG, CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, CORESIGHT_DEV_SUBTYPE_LINK_FIFO, }; enum coresight_dev_subtype_source { - CORESIGHT_DEV_SUBTYPE_SOURCE_NONE, CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, }; enum coresight_dev_subtype_helper { - CORESIGHT_DEV_SUBTYPE_HELPER_NONE, CORESIGHT_DEV_SUBTYPE_HELPER_CATU, }; -- cgit v1.2.3