From 5d58c6207c300340151931ad9c2cdea2d1685dc4 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Fri, 26 Jun 2015 09:32:59 +0100 Subject: iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT The arm64 CPU architecture defines TCR[8:11] as holding the inner and outer memory attributes for TTBR0. This patch fixes the ARM SMMUv3 driver to pack these bits into the context descriptor, rather than picking up the TTBR1 attributes as it currently does. Signed-off-by: Zhen Lei Signed-off-by: Will Deacon --- drivers/iommu/arm-smmu-v3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/iommu') diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 6b1ae4e09616..98e987a3ed3a 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -269,10 +269,10 @@ #define ARM64_TCR_TG0_SHIFT 14 #define ARM64_TCR_TG0_MASK 0x3UL #define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8 -#define ARM64_TCR_IRGN0_SHIFT 24 +#define ARM64_TCR_IRGN0_SHIFT 8 #define ARM64_TCR_IRGN0_MASK 0x3UL #define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10 -#define ARM64_TCR_ORGN0_SHIFT 26 +#define ARM64_TCR_ORGN0_SHIFT 10 #define ARM64_TCR_ORGN0_MASK 0x3UL #define CTXDESC_CD_0_TCR_SH0_SHIFT 12 #define ARM64_TCR_SH0_SHIFT 12 -- cgit v1.2.3