From 3d03641cb4ea050f969dd3ab34113adb95287f36 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Sun, 5 Oct 2014 12:35:13 +0300 Subject: net/mlx4_en: Avoid a cache line miss in TX completion for single frag skb's Add frag0_dma/frag0_byte_count into mlx4_en_tx_info to avoid a cache line miss in TX completion for frames having one dma element. (We avoid reading back the tx descriptor) Note this could be extended to 2/3 dma elements later, as we have free room in mlx4_en_tx_info Also, mlx4_en_free_tx_desc() no longer accesses skb_shinfo(). We use a new nr_maps fields in mlx4_en_tx_info to avoid 2 or 3 cache misses. Signed-off-by: Eric Dumazet Signed-off-by: Amir Vadai Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlx4/mlx4_en.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/net/ethernet/mellanox/mlx4/mlx4_en.h') diff --git a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h index ab34461e628c..a90403000577 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h +++ b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h @@ -216,12 +216,15 @@ enum cq_type { struct mlx4_en_tx_info { struct sk_buff *skb; + dma_addr_t map0_dma; + u32 map0_byte_count; u32 nr_txbb; u32 nr_bytes; u8 linear; u8 data_offset; u8 inl; u8 ts_requested; + u8 nr_maps; } ____cacheline_aligned_in_smp; -- cgit v1.2.3