From 7ccc83b0fc69d5b18602aa250c10be0d3ae920c6 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Mon, 15 Aug 2011 18:45:54 +0200 Subject: carl9170: fix timekeeping for HW_COUNTER firmwares AR9170_PWR_REG_PLL_ADDAC is used to set the main clock divisor which affects the AHB/CPU speed. Because this would interfere with the firmware internal timekeeping, the function has to be moved into the firmware. Signed-off-by: Christian Lamparter Signed-off-by: John W. Linville --- drivers/net/wireless/ath/carl9170/phy.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers/net/wireless/ath/carl9170/phy.c') diff --git a/drivers/net/wireless/ath/carl9170/phy.c b/drivers/net/wireless/ath/carl9170/phy.c index aa147a9120b6..8635c5c8463c 100644 --- a/drivers/net/wireless/ath/carl9170/phy.c +++ b/drivers/net/wireless/ath/carl9170/phy.c @@ -578,11 +578,10 @@ static int carl9170_init_phy(struct ar9170 *ar, enum ieee80211_band band) if (err) return err; - /* XXX: remove magic! */ - if (is_2ghz) - err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5163); - else - err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5143); + if (!ar->fw.hw_counters) { + err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, + is_2ghz ? 0x5163 : 0x5143); + } return err; } -- cgit v1.2.3