From 86b4ad7d67b26973838b7f1d4428aba9483cb5ce Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 24 Aug 2023 11:44:32 -0500 Subject: PCI: Fix typos in docs and comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix typos in docs and comments. Link: https://lore.kernel.org/r/20230824193712.542167-11-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Randy Dunlap Reviewed-by: Ilpo Järvinen --- drivers/pci/controller/cadence/pcie-cadence.h | 2 +- drivers/pci/endpoint/functions/pci-epf-vntb.c | 32 +++++++++++++-------------- drivers/pci/msi/irqdomain.c | 4 ++-- drivers/pci/p2pdma.c | 2 +- drivers/pci/pci.c | 2 +- drivers/pci/probe.c | 2 +- drivers/pci/quirks.c | 8 +++---- drivers/pci/setup-bus.c | 2 +- 8 files changed, 27 insertions(+), 27 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 190786e47df9..373cb50fcd15 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -32,7 +32,7 @@ #define CDNS_PCIE_LM_ID_SUBSYS(sub) \ (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) -/* Root Port Requestor ID Register */ +/* Root Port Requester ID Register */ #define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) #define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) #define CDNS_PCIE_LM_RP_RID_SHIFT 0 diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c index c8b423c3c26e..3f60128560ed 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -986,22 +986,22 @@ static struct config_group *epf_ntb_add_cfs(struct pci_epf *epf, /*==== virtual PCI bus driver, which only load virtual NTB PCI driver ====*/ static u32 pci_space[] = { - 0xffffffff, /*DeviceID, Vendor ID*/ - 0, /*Status, Command*/ - 0xffffffff, /*Class code, subclass, prog if, revision id*/ - 0x40, /*bist, header type, latency Timer, cache line size*/ - 0, /*BAR 0*/ - 0, /*BAR 1*/ - 0, /*BAR 2*/ - 0, /*BAR 3*/ - 0, /*BAR 4*/ - 0, /*BAR 5*/ - 0, /*Cardbus cis point*/ - 0, /*Subsystem ID Subystem vendor id*/ - 0, /*ROM Base Address*/ - 0, /*Reserved, Cap. Point*/ - 0, /*Reserved,*/ - 0, /*Max Lat, Min Gnt, interrupt pin, interrupt line*/ + 0xffffffff, /* Device ID, Vendor ID */ + 0, /* Status, Command */ + 0xffffffff, /* Base Class, Subclass, Prog Intf, Revision ID */ + 0x40, /* BIST, Header Type, Latency Timer, Cache Line Size */ + 0, /* BAR 0 */ + 0, /* BAR 1 */ + 0, /* BAR 2 */ + 0, /* BAR 3 */ + 0, /* BAR 4 */ + 0, /* BAR 5 */ + 0, /* Cardbus CIS Pointer */ + 0, /* Subsystem ID, Subsystem Vendor ID */ + 0, /* ROM Base Address */ + 0, /* Reserved, Capabilities Pointer */ + 0, /* Reserved */ + 0, /* Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line */ }; static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c index e33bcc872699..c8be056c248d 100644 --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -336,7 +336,7 @@ bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask, if (!irq_domain_is_msi_parent(domain)) { /* * For "global" PCI/MSI interrupt domains the associated - * msi_domain_info::flags is the authoritive source of + * msi_domain_info::flags is the authoritative source of * information. */ info = domain->host_data; @@ -344,7 +344,7 @@ bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask, } else { /* * For MSI parent domains the supported feature set - * is avaliable in the parent ops. This makes checks + * is available in the parent ops. This makes checks * possible before actually instantiating the * per device domain because the parent is never * expanding the PCI/MSI functionality. diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c index ec04d0ed157b..fa7370f9561a 100644 --- a/drivers/pci/p2pdma.c +++ b/drivers/pci/p2pdma.c @@ -435,7 +435,7 @@ static const struct pci_p2pdma_whitelist_entry { /* Intel Xeon E7 v3/Xeon E5 v3/Core i7 */ {PCI_VENDOR_ID_INTEL, 0x2f00, REQ_SAME_HOST_BRIDGE}, {PCI_VENDOR_ID_INTEL, 0x2f01, REQ_SAME_HOST_BRIDGE}, - /* Intel SkyLake-E */ + /* Intel Skylake-E */ {PCI_VENDOR_ID_INTEL, 0x2030, 0}, {PCI_VENDOR_ID_INTEL, 0x2031, 0}, {PCI_VENDOR_ID_INTEL, 0x2032, 0}, diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 6b62795425a7..749ef90c623d 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1290,7 +1290,7 @@ end: * * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register * to confirm the state change, restore its BARs if they might be lost and - * reconfigure ASPM in acordance with the new power state. + * reconfigure ASPM in accordance with the new power state. * * If pci_restore_state() is going to be called right after a power state change * to D0, it is more efficient to use pci_power_up() directly instead of this diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 31fb02fbb2cc..deb5286f8533 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2136,7 +2136,7 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev) { struct pci_dev *root; - /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ + /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */ if (dev->is_virtfn) return; diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 321156ca273d..e2afa3918367 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -362,7 +362,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_d #endif /* - * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear + * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear * for some HT machines to use C4 w/o hanging. */ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) @@ -375,7 +375,7 @@ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) pm1a = inw(pmbase); if (pm1a & 0x10) { - pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); + pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); outw(0x10, pmbase); } } @@ -3073,7 +3073,7 @@ static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) /* * HT MSI mapping should be disabled on devices that are below - * a non-Hypertransport host bridge. Locate the host bridge... + * a non-HyperTransport host bridge. Locate the host bridge. */ host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, PCI_DEVFN(0, 0)); @@ -5729,7 +5729,7 @@ int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) /* * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between * NT endpoints via the internal switch fabric. These IDs replace the - * originating requestor ID TLPs which access host memory on peer NTB + * originating Requester ID TLPs which access host memory on peer NTB * ports. Therefore, all proxy IDs must be aliased to the NTB device * to permit access when the IOMMU is turned on. */ diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index fdeb121e9175..dae490f25641 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1799,7 +1799,7 @@ static void remove_dev_resources(struct pci_dev *dev, struct resource *io, * Make sure prefetchable memory is reduced from * the correct resource. Specifically we put 32-bit * prefetchable memory in non-prefetchable window - * if there is an 64-bit pretchable window. + * if there is an 64-bit prefetchable window. * * See comments in __pci_bus_size_bridges() for * more information. -- cgit v1.2.3