From a05b6d5135ec3e65520ae0eaa1b24d4c6549424e Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Fri, 14 Jul 2023 10:38:36 +0530 Subject: phy: qcom-qmp-pcie: add support for sa8775p Add support for dual and four lane PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar Link: https://lore.kernel.org/r/1689311319-22054-5-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h index c7b12c1fb7f5..cf91154eed13 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h @@ -19,6 +19,7 @@ /* Only for QMP V5_20 PHY - RX registers */ #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c +#define QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3 0x01c #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 @@ -80,5 +81,6 @@ #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 +#define QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x238 #endif -- cgit v1.2.3