From 5cde07abcbc57b3430b044cb2cf028d97d7a7254 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 15 Jun 2015 13:54:29 +0900 Subject: pinctrl: samsung: Remove old unused defines Since 9a2c1c3b91aa ("pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes") the defines for GPIO group and function names are not used anywhere in the driver. Signed-off-by: Krzysztof Kozlowski Inspired-by: Dan Carpenter Signed-off-by: Linus Walleij --- drivers/pinctrl/samsung/pinctrl-samsung.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 3dd5a3b2ac62..c760bf43d116 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -33,11 +33,6 @@ #include "../core.h" #include "pinctrl-samsung.h" -#define GROUP_SUFFIX "-grp" -#define GSUFFIX_LEN sizeof(GROUP_SUFFIX) -#define FUNCTION_SUFFIX "-mux" -#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX) - /* list of all possible config options supported */ static struct pin_config { const char *property; -- cgit v1.2.3 From 27aa2e3a3c99d3319de12ada0d292e33f5831e60 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 8 Jul 2015 15:12:06 +0200 Subject: pinctrl: abx500: remove strict mode Commit a21763a0b1e5a5ab8310f581886d04beadc16616 "pinctrl: nomadik: activate strict mux mode" put all Nomadik pin controllers to strict mode. This was not good on the Snowball platform: the muxing of GPIOs to different pins is done with hogs in the DTS file, and then these GPIOs are used by offset, relying on hogs to mux the pins. Since that means the pin controller "owns" the pins and at the same time we have a GPIO user, this pin controller is by definition not strict. Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-abx500.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 557d0f2a3031..97681fac082e 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -787,7 +787,6 @@ static const struct pinmux_ops abx500_pinmux_ops = { .set_mux = abx500_pmx_set, .gpio_request_enable = abx500_gpio_request_enable, .gpio_disable_free = abx500_gpio_disable_free, - .strict = true, }; static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) -- cgit v1.2.3 From 61bb3aef92a4d102382f399eafccd5c72be6fdf2 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 26 Jun 2015 01:40:56 +0300 Subject: sh-pfc: fix sparse GPIOs for R-Car SoCs The PFC driver causes the kernel to hang on the R-Car gen2 SoC based boards when the CPU_ALL_PORT() macro is fixed to reflect the reality, i.e. when the GPIO space becomes actually sparse. This happens because the _GP_GPIO() macro includes an indexed initializer which causes the "holes" (array entries filled with all 0s) between the groups of the existing GPIOs; and the driver can't cope with that. There seems to be no reason to use the indexed initializer, so we can remove the index specifier and so avoid the "holes". Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart Tested-by: Geert Uytterhoeven Signed-off-by: Linus Walleij --- drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index c7508d5f6886..0874cfee6889 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -224,7 +224,7 @@ struct sh_pfc_soc_info { /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ #define _GP_GPIO(bank, _pin, _name, sfx) \ - [(bank * 32) + _pin] = { \ + { \ .pin = (bank * 32) + _pin, \ .name = __stringify(_name), \ .enum_id = _name##_DATA, \ -- cgit v1.2.3 From c10372e615b8f790d30cbfcf59e43908ca42bf1a Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 6 Jul 2015 18:13:37 +0300 Subject: pinctrl: single: ensure pcs irq will not be forced threaded The PSC IRQ is requested using request_irq() API and as result it can be forced to be threaded IRQ in RT-Kernel if PCS_QUIRK_HAS_SHARED_IRQ is enabled for pinctrl domain. As result, following 'possible irq lock inversion dependency' report can be seen: ========================================================= [ INFO: possible irq lock inversion dependency detected ] 3.14.43-rt42-00360-g96ff499-dirty #24 Not tainted --------------------------------------------------------- irq/369-pinctrl/927 just changed the state of lock: (&pcs->lock){+.....}, at: [] pcs_irq_handle+0x48/0x9c but this lock was taken by another, HARDIRQ-safe lock in the past: (&irq_desc_lock_class){-.....} and interrupts could create inverse lock ordering between them. other info that might help us debug this: Possible interrupt unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&pcs->lock); local_irq_disable(); lock(&irq_desc_lock_class); lock(&pcs->lock); lock(&irq_desc_lock_class); *** DEADLOCK *** no locks held by irq/369-pinctrl/927. the shortest dependencies between 2nd lock and 1st lock: -> (&irq_desc_lock_class){-.....} ops: 58724 { IN-HARDIRQ-W at: [] lock_acquire+0x9c/0x158 [] _raw_spin_lock+0x48/0x58 [] handle_fasteoi_irq+0x24/0x15c [] generic_handle_irq+0x3c/0x4c [] handle_IRQ+0x50/0xa0 [] gic_handle_irq+0x3c/0x6c [] __irq_svc+0x44/0x8c [] arch_cpu_idle+0x40/0x4c [] cpu_startup_entry+0x270/0x2e0 [] rest_init+0xd4/0xe4 [] start_kernel+0x3d0/0x3dc [<80008084>] 0x80008084 INITIAL USE at: [] lock_acquire+0x9c/0x158 [] _raw_spin_lock_irqsave+0x54/0x68 [] __irq_get_desc_lock+0x64/0xa4 [] irq_set_chip+0x30/0x78 [] irq_set_chip_and_handler_name+0x24/0x3c [] gic_irq_domain_map+0x48/0xb4 [] irq_domain_associate+0x84/0x1d4 [] irq_create_mapping+0x80/0x11c [] irq_create_of_mapping+0x80/0x120 [] irq_of_parse_and_map+0x34/0x3c [] omap_dm_timer_init_one+0x90/0x30c [] omap5_realtime_timer_init+0x8c/0x48c [] time_init+0x28/0x38 [] start_kernel+0x240/0x3dc [<80008084>] 0x80008084 } ... key at: [] irq_desc_lock_class+0x0/0x8 ... acquired at: [] _raw_spin_lock+0x48/0x58 [] pcs_irq_unmask+0x58/0xa0 [] irq_enable+0x38/0x48 [] irq_startup+0x78/0x7c [] __setup_irq+0x4a8/0x4f4 [] request_threaded_irq+0xb8/0x138 [] omap_8250_startup+0x4c/0x148 [] serial8250_startup+0x24/0x30 [] uart_startup.part.9+0x5c/0x1b4 [] uart_open+0xf4/0x16c [] tty_open+0x170/0x61c [] chrdev_open+0xbc/0x1b4 [] do_dentry_open+0x1e8/0x2bc [] finish_open+0x44/0x5c [] do_last.isra.47+0x710/0xca0 [] path_openat+0xc4/0x640 [] do_filp_open+0x3c/0x98 [] do_sys_open+0x114/0x1d8 [] SyS_open+0x28/0x2c [] kernel_init_freeable+0x168/0x1e4 [] kernel_init+0x1c/0xf8 [] ret_from_fork+0x14/0x20 -> (&pcs->lock){+.....} ops: 65 { HARDIRQ-ON-W at: [] lock_acquire+0x9c/0x158 [] _raw_spin_lock+0x48/0x58 [] pcs_irq_handle+0x48/0x9c [] pcs_irq_handler+0x1c/0x28 [] irq_forced_thread_fn+0x30/0x74 [] irq_thread+0x158/0x1c4 [] kthread+0xd4/0xe8 [] ret_from_fork+0x14/0x20 INITIAL USE at: [] lock_acquire+0x9c/0x158 [] _raw_spin_lock_irqsave+0x54/0x68 [] pcs_enable+0x7c/0xe8 [] pinmux_enable_setting+0x178/0x220 [] pinctrl_select_state+0x110/0x194 [] pinctrl_bind_pins+0x7c/0x108 [] driver_probe_device+0x70/0x254 [] __driver_attach+0x9c/0xa0 [] bus_for_each_dev+0x78/0xac [] driver_attach+0x2c/0x30 [] bus_add_driver+0x15c/0x204 [] driver_register+0x88/0x108 [] __platform_driver_register+0x64/0x6c [] omap_hsmmc_driver_init+0x1c/0x20 [] do_one_initcall+0x110/0x170 [] kernel_init_freeable+0x140/0x1e4 [] kernel_init+0x1c/0xf8 [] ret_from_fork+0x14/0x20 } ... key at: [] __key.18572+0x0/0x8 ... acquired at: [] mark_lock+0x388/0x76c [] __lock_acquire+0x6d0/0x1f98 [] lock_acquire+0x9c/0x158 [] _raw_spin_lock+0x48/0x58 [] pcs_irq_handle+0x48/0x9c [] pcs_irq_handler+0x1c/0x28 [] irq_forced_thread_fn+0x30/0x74 [] irq_thread+0x158/0x1c4 [] kthread+0xd4/0xe8 [] ret_from_fork+0x14/0x20 stack backtrace: CPU: 1 PID: 927 Comm: irq/369-pinctrl Not tainted 3.14.43-rt42-00360-g96ff499-dirty #24 [] (unwind_backtrace) from [] (show_stack+0x20/0x24) [] (show_stack) from [] (dump_stack+0x84/0xd0) [] (dump_stack) from [] (print_irq_inversion_bug+0x1d0/0x21c) [] (print_irq_inversion_bug) from [] (check_usage_backwards+0xb4/0x11c) [] (check_usage_backwards) from [] (mark_lock+0x388/0x76c) [] (mark_lock) from [] (__lock_acquire+0x6d0/0x1f98) [] (__lock_acquire) from [] (lock_acquire+0x9c/0x158) [] (lock_acquire) from [] (_raw_spin_lock+0x48/0x58) [] (_raw_spin_lock) from [] (pcs_irq_handle+0x48/0x9c) [] (pcs_irq_handle) from [] (pcs_irq_handler+0x1c/0x28) [] (pcs_irq_handler) from [] (irq_forced_thread_fn+0x30/0x74) [] (irq_forced_thread_fn) from [] (irq_thread+0x158/0x1c4) [] (irq_thread) from [] (kthread+0xd4/0xe8) [] (kthread) from [] (ret_from_fork+0x14/0x20) To fix it use IRQF_NO_THREAD to ensure that pcs irq will not be forced threaded. Cc: Tony Lindgren Cc: Sebastian Andrzej Siewior Signed-off-by: Grygorii Strashko Acked-by: Tony Lindgren Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index b2de09d3b1a0..0b8d480171a3 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1760,7 +1760,8 @@ static int pcs_irq_init_chained_handler(struct pcs_device *pcs, int res; res = request_irq(pcs_soc->irq, pcs_irq_handler, - IRQF_SHARED | IRQF_NO_SUSPEND, + IRQF_SHARED | IRQF_NO_SUSPEND | + IRQF_NO_THREAD, name, pcs_soc); if (res) { pcs_soc->irq = -1; -- cgit v1.2.3 From 714b1dd8f72e39ef4bc0f38f7f341bb1d57d98bf Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Tue, 30 Jun 2015 12:35:39 +0100 Subject: pinctrl: bcm2835: Clear the event latch register when disabling interrupts It's possible to hit a race condition if interrupts are generated on a GPIO pin when the IRQ line in question is being disabled. If the interrupt is freed, bcm2835_gpio_irq_disable() is called which disables the event generation sources (edge, level). If an event occurred between the last disabling of hard IRQs and the write to the event source registers, a bit would be set in the GPIO event detect register (GPEDSn) which goes unacknowledged by bcm2835_gpio_irq_handler() so Linux complains loudly. There is no per-GPIO mask register, so when disabling GPIO interrupts write 1 to the relevant bit in GPEDSn to clear out any stale events. Signed-off-by: Jonathan Bell Acked-by: Stephen Warren Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index efcf2a2b3975..6177315ab74e 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -473,6 +473,8 @@ static void bcm2835_gpio_irq_disable(struct irq_data *data) spin_lock_irqsave(&pc->irq_lock[bank], flags); bcm2835_gpio_irq_config(pc, gpio, false); + /* Clear events that were latched prior to clearing event sources */ + bcm2835_gpio_set_bit(pc, GPEDS0, gpio); clear_bit(offset, &pc->enabled_irq_map[bank]); spin_unlock_irqrestore(&pc->irq_lock[bank], flags); } -- cgit v1.2.3 From 9571b25df1dbf4db17191b54f59734e8b77fd591 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 17 Jul 2015 09:38:43 +0200 Subject: Subject: pinctrl: imx1-core: Fix debug output in .pin_config_set callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit imx1_pinconf_set assumes that the array of pins in struct imx1_pinctrl_soc_info can be indexed by pin id to get the pinctrl_pin_desc for a pin. This used to be correct up to commit 607af165c047 which removed some entries from the array and so made it wrong to access the array by pin id. The result of this bug is a wrong pin name in the output for small pin ids and an oops for the bigger ones. This patch is the result of a discussion that includes patches by Markus Pargmann and Chris Ruehl. Fixes: 607af165c047 ("pinctrl: i.MX27: Remove nonexistent pad definitions") Cc: stable@vger.kernel.org Reported-by: Chris Ruehl Signed-off-by: Uwe Kleine-König Reviewed-by: Markus Pargmann Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx1-core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index 5fd4437cee15..88a7fac11bd4 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -403,14 +403,13 @@ static int imx1_pinconf_set(struct pinctrl_dev *pctldev, unsigned num_configs) { struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx1_pinctrl_soc_info *info = ipctl->info; int i; for (i = 0; i != num_configs; ++i) { imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN); dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n", - info->pins[pin_id].name); + pin_desc_get(pctldev, pin_id)->name); } return 0; -- cgit v1.2.3 From 681ccdcc756f17f847beba5ac4cd3d03e0949489 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Wed, 15 Jul 2015 00:25:26 +0200 Subject: pinctrl: lpc18xx: fix schmitt trigger setup The param_val variable is what determines if schmitt trigger is enabled on a pin or not. A typo here mean that schmitt trigger was always enabled for standard and i2c pins. Signed-off-by: Joachim Eastwood Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-lpc18xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index ef0b697639a7..347c763a6a78 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -823,7 +823,7 @@ static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - if (param) + if (param_val) *reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift); else *reg |= (LPC18XX_SCU_I2C0_ZIF << shift); @@ -876,7 +876,7 @@ static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - if (param) + if (param_val) *reg &= ~LPC18XX_SCU_PIN_ZIF; else *reg |= LPC18XX_SCU_PIN_ZIF; -- cgit v1.2.3