From bbb8eb3cb06f66866726ddacfbf7c1411a40565d Mon Sep 17 00:00:00 2001 From: Dylan Hung Date: Tue, 18 Jul 2023 14:26:16 +0800 Subject: dt-bindings: clock: ast2600: Add I3C and MAC reset definitions Add reset definitions of AST2600 I3C and MAC controllers. In the case of the I3C reset, since there is no reset-line hardware available for `ASPEED_RESET_I3C_DMA`, a new macro `ASPEED_RESET_I3C` with the same ID is introduced to provide a more accurate representation of the hardware. The old macro `ASPEED_RESET_I3C_DMA` is kept to provide backward compatibility. Signed-off-by: Dylan Hung Link: https://lore.kernel.org/r/20230718062616.2822339-1-dylan_hung@aspeedtech.com Acked-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- include/dt-bindings/clock/ast2600-clock.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index e149eee61588..712782177c90 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -90,7 +90,19 @@ /* Only list resets here that are not part of a clock gate + reset pair */ #define ASPEED_RESET_ADC 55 #define ASPEED_RESET_JTAG_MASTER2 54 + +#define ASPEED_RESET_MAC4 53 +#define ASPEED_RESET_MAC3 52 + +#define ASPEED_RESET_I3C5 45 +#define ASPEED_RESET_I3C4 44 +#define ASPEED_RESET_I3C3 43 +#define ASPEED_RESET_I3C2 42 +#define ASPEED_RESET_I3C1 41 +#define ASPEED_RESET_I3C0 40 +#define ASPEED_RESET_I3C 39 #define ASPEED_RESET_I3C_DMA 39 + #define ASPEED_RESET_PWM 37 #define ASPEED_RESET_PECI 36 #define ASPEED_RESET_MII 35 -- cgit v1.2.3 From 2fe182dd2783c870cb21f20732ff62f9cbb2451a Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 28 Jun 2023 14:17:22 +0800 Subject: dt-bindings: clock: imx93: Add PDM IPG clk Add PDM IPG clk. Reviewed-by: Shengjiu Wang Signed-off-by: Chancel Liu Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230628061724.2056520-1-ping.bai@nxp.com Signed-off-by: Abel Vesa --- include/dt-bindings/clock/imx93-clock.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 35a1f62053a5..787c9e74dc96 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -203,6 +203,7 @@ #define IMX93_CLK_ARM_PLL 198 #define IMX93_CLK_A55_SEL 199 #define IMX93_CLK_A55_CORE 200 -#define IMX93_CLK_END 201 +#define IMX93_CLK_PDM_IPG 201 +#define IMX93_CLK_END 202 #endif -- cgit v1.2.3 From 9f08d334969ba3e2ced6769a13372b153256b2d7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:19 +0300 Subject: dt-bindings: clock: drop qcom,lcc-mdm9615 header file The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230512211727.3445575-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/lcc-mdm9615.c | 2 +- include/dt-bindings/clock/qcom,lcc-mdm9615.h | 44 ---------------------------- 2 files changed, 1 insertion(+), 45 deletions(-) delete mode 100644 include/dt-bindings/clock/qcom,lcc-mdm9615.h (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c index 8d243e880d95..c17caffdc349 100644 --- a/drivers/clk/qcom/lcc-mdm9615.c +++ b/drivers/clk/qcom/lcc-mdm9615.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include "common.h" #include "clk-regmap.h" diff --git a/include/dt-bindings/clock/qcom,lcc-mdm9615.h b/include/dt-bindings/clock/qcom,lcc-mdm9615.h deleted file mode 100644 index 299338ee1d88..000000000000 --- a/include/dt-bindings/clock/qcom,lcc-mdm9615.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Copyright (c) BayLibre, SAS. - * Author : Neil Armstrong - */ - -#ifndef _DT_BINDINGS_CLK_LCC_MDM9615_H -#define _DT_BINDINGS_CLK_LCC_MDM9615_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SLIMBUS_SRC 9 -#define AUDIO_SLIMBUS_CLK 10 -#define SPS_SLIMBUS_CLK 11 -#define CODEC_I2S_MIC_OSR_SRC 12 -#define CODEC_I2S_MIC_OSR_CLK 13 -#define CODEC_I2S_MIC_DIV_CLK 14 -#define CODEC_I2S_MIC_BIT_DIV_CLK 15 -#define CODEC_I2S_MIC_BIT_CLK 16 -#define SPARE_I2S_MIC_OSR_SRC 17 -#define SPARE_I2S_MIC_OSR_CLK 18 -#define SPARE_I2S_MIC_DIV_CLK 19 -#define SPARE_I2S_MIC_BIT_DIV_CLK 20 -#define SPARE_I2S_MIC_BIT_CLK 21 -#define CODEC_I2S_SPKR_OSR_SRC 22 -#define CODEC_I2S_SPKR_OSR_CLK 23 -#define CODEC_I2S_SPKR_DIV_CLK 24 -#define CODEC_I2S_SPKR_BIT_DIV_CLK 25 -#define CODEC_I2S_SPKR_BIT_CLK 26 -#define SPARE_I2S_SPKR_OSR_SRC 27 -#define SPARE_I2S_SPKR_OSR_CLK 28 -#define SPARE_I2S_SPKR_DIV_CLK 29 -#define SPARE_I2S_SPKR_BIT_DIV_CLK 30 -#define SPARE_I2S_SPKR_BIT_CLK 31 - -#endif -- cgit v1.2.3 From 9ce85552784368b62cc68009451440e93298e0b4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:24 +0200 Subject: dt-bindings: clk: gxbb-clkc: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every gxbb-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-7-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb.h | 76 ----------------------------------- include/dt-bindings/clock/gxbb-clkc.h | 65 ++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 76 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 6751cda25986..798ffb911103 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -112,82 +112,6 @@ #define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ #define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ -/* - * CLKID index values - * - * These indices are entirely contrived and do not map onto the hardware. - * It has now been decided to expose everything by default in the DT header: - * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want - * to expose, such as the internal muxes and dividers of composite clocks, - * will remain defined here. - */ -/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */ -#define CLKID_MPEG_SEL 10 -#define CLKID_MPEG_DIV 11 -#define CLKID_SAR_ADC_DIV 99 -#define CLKID_MALI_0_DIV 101 -#define CLKID_MALI_1_DIV 104 -#define CLKID_CTS_AMCLK_SEL 108 -#define CLKID_CTS_AMCLK_DIV 109 -#define CLKID_CTS_MCLK_I958_SEL 111 -#define CLKID_CTS_MCLK_I958_DIV 112 -#define CLKID_32K_CLK_SEL 115 -#define CLKID_32K_CLK_DIV 116 -#define CLKID_SD_EMMC_A_CLK0_SEL 117 -#define CLKID_SD_EMMC_A_CLK0_DIV 118 -#define CLKID_SD_EMMC_B_CLK0_SEL 120 -#define CLKID_SD_EMMC_B_CLK0_DIV 121 -#define CLKID_SD_EMMC_C_CLK0_SEL 123 -#define CLKID_SD_EMMC_C_CLK0_DIV 124 -#define CLKID_VPU_0_DIV 127 -#define CLKID_VPU_1_DIV 130 -#define CLKID_VAPB_0_DIV 134 -#define CLKID_VAPB_1_DIV 137 -#define CLKID_HDMI_PLL_PRE_MULT 141 -#define CLKID_MPLL0_DIV 142 -#define CLKID_MPLL1_DIV 143 -#define CLKID_MPLL2_DIV 144 -#define CLKID_MPLL_PREDIV 145 -#define CLKID_FCLK_DIV2_DIV 146 -#define CLKID_FCLK_DIV3_DIV 147 -#define CLKID_FCLK_DIV4_DIV 148 -#define CLKID_FCLK_DIV5_DIV 149 -#define CLKID_FCLK_DIV7_DIV 150 -#define CLKID_VDEC_1_SEL 151 -#define CLKID_VDEC_1_DIV 152 -#define CLKID_VDEC_HEVC_SEL 154 -#define CLKID_VDEC_HEVC_DIV 155 -#define CLKID_GEN_CLK_SEL 157 -#define CLKID_GEN_CLK_DIV 158 -#define CLKID_FIXED_PLL_DCO 160 -#define CLKID_HDMI_PLL_DCO 161 -#define CLKID_HDMI_PLL_OD 162 -#define CLKID_HDMI_PLL_OD2 163 -#define CLKID_SYS_PLL_DCO 164 -#define CLKID_GP0_PLL_DCO 165 -#define CLKID_VID_PLL_SEL 167 -#define CLKID_VID_PLL_DIV 168 -#define CLKID_VCLK_SEL 169 -#define CLKID_VCLK2_SEL 170 -#define CLKID_VCLK_INPUT 171 -#define CLKID_VCLK2_INPUT 172 -#define CLKID_VCLK_DIV 173 -#define CLKID_VCLK2_DIV 174 -#define CLKID_VCLK_DIV2_EN 177 -#define CLKID_VCLK_DIV4_EN 178 -#define CLKID_VCLK_DIV6_EN 179 -#define CLKID_VCLK_DIV12_EN 180 -#define CLKID_VCLK2_DIV2_EN 181 -#define CLKID_VCLK2_DIV4_EN 182 -#define CLKID_VCLK2_DIV6_EN 183 -#define CLKID_VCLK2_DIV12_EN 184 -#define CLKID_CTS_ENCI_SEL 195 -#define CLKID_CTS_ENCP_SEL 196 -#define CLKID_CTS_VDAC_SEL 197 -#define CLKID_HDMI_TX_SEL 198 -#define CLKID_HDMI_SEL 203 -#define CLKID_HDMI_DIV 204 - /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index 4073eb7a9da1..c0ce5e9c4151 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -15,6 +15,8 @@ #define CLKID_FCLK_DIV5 7 #define CLKID_FCLK_DIV7 8 #define CLKID_GP0_PLL 9 +#define CLKID_MPEG_SEL 10 +#define CLKID_MPEG_DIV 11 #define CLKID_CLK81 12 #define CLKID_MPLL0 13 #define CLKID_MPLL1 14 @@ -102,35 +104,92 @@ #define CLKID_SD_EMMC_C 96 #define CLKID_SAR_ADC_CLK 97 #define CLKID_SAR_ADC_SEL 98 +#define CLKID_SAR_ADC_DIV 99 #define CLKID_MALI_0_SEL 100 +#define CLKID_MALI_0_DIV 101 #define CLKID_MALI_0 102 #define CLKID_MALI_1_SEL 103 +#define CLKID_MALI_1_DIV 104 #define CLKID_MALI_1 105 #define CLKID_MALI 106 #define CLKID_CTS_AMCLK 107 +#define CLKID_CTS_AMCLK_SEL 108 +#define CLKID_CTS_AMCLK_DIV 109 #define CLKID_CTS_MCLK_I958 110 +#define CLKID_CTS_MCLK_I958_SEL 111 +#define CLKID_CTS_MCLK_I958_DIV 112 #define CLKID_CTS_I958 113 #define CLKID_32K_CLK 114 +#define CLKID_32K_CLK_SEL 115 +#define CLKID_32K_CLK_DIV 116 +#define CLKID_SD_EMMC_A_CLK0_SEL 117 +#define CLKID_SD_EMMC_A_CLK0_DIV 118 #define CLKID_SD_EMMC_A_CLK0 119 +#define CLKID_SD_EMMC_B_CLK0_SEL 120 +#define CLKID_SD_EMMC_B_CLK0_DIV 121 #define CLKID_SD_EMMC_B_CLK0 122 +#define CLKID_SD_EMMC_C_CLK0_SEL 123 +#define CLKID_SD_EMMC_C_CLK0_DIV 124 #define CLKID_SD_EMMC_C_CLK0 125 #define CLKID_VPU_0_SEL 126 +#define CLKID_VPU_0_DIV 127 #define CLKID_VPU_0 128 #define CLKID_VPU_1_SEL 129 +#define CLKID_VPU_1_DIV 130 #define CLKID_VPU_1 131 #define CLKID_VPU 132 #define CLKID_VAPB_0_SEL 133 +#define CLKID_VAPB_0_DIV 134 #define CLKID_VAPB_0 135 #define CLKID_VAPB_1_SEL 136 +#define CLKID_VAPB_1_DIV 137 #define CLKID_VAPB_1 138 #define CLKID_VAPB_SEL 139 #define CLKID_VAPB 140 +#define CLKID_HDMI_PLL_PRE_MULT 141 +#define CLKID_MPLL0_DIV 142 +#define CLKID_MPLL1_DIV 143 +#define CLKID_MPLL2_DIV 144 +#define CLKID_MPLL_PREDIV 145 +#define CLKID_FCLK_DIV2_DIV 146 +#define CLKID_FCLK_DIV3_DIV 147 +#define CLKID_FCLK_DIV4_DIV 148 +#define CLKID_FCLK_DIV5_DIV 149 +#define CLKID_FCLK_DIV7_DIV 150 +#define CLKID_VDEC_1_SEL 151 +#define CLKID_VDEC_1_DIV 152 #define CLKID_VDEC_1 153 +#define CLKID_VDEC_HEVC_SEL 154 +#define CLKID_VDEC_HEVC_DIV 155 #define CLKID_VDEC_HEVC 156 +#define CLKID_GEN_CLK_SEL 157 +#define CLKID_GEN_CLK_DIV 158 #define CLKID_GEN_CLK 159 +#define CLKID_FIXED_PLL_DCO 160 +#define CLKID_HDMI_PLL_DCO 161 +#define CLKID_HDMI_PLL_OD 162 +#define CLKID_HDMI_PLL_OD2 163 +#define CLKID_SYS_PLL_DCO 164 +#define CLKID_GP0_PLL_DCO 165 #define CLKID_VID_PLL 166 +#define CLKID_VID_PLL_SEL 167 +#define CLKID_VID_PLL_DIV 168 +#define CLKID_VCLK_SEL 169 +#define CLKID_VCLK2_SEL 170 +#define CLKID_VCLK_INPUT 171 +#define CLKID_VCLK2_INPUT 172 +#define CLKID_VCLK_DIV 173 +#define CLKID_VCLK2_DIV 174 #define CLKID_VCLK 175 #define CLKID_VCLK2 176 +#define CLKID_VCLK_DIV2_EN 177 +#define CLKID_VCLK_DIV4_EN 178 +#define CLKID_VCLK_DIV6_EN 179 +#define CLKID_VCLK_DIV12_EN 180 +#define CLKID_VCLK2_DIV2_EN 181 +#define CLKID_VCLK2_DIV4_EN 182 +#define CLKID_VCLK2_DIV6_EN 183 +#define CLKID_VCLK2_DIV12_EN 184 #define CLKID_VCLK_DIV1 185 #define CLKID_VCLK_DIV2 186 #define CLKID_VCLK_DIV4 187 @@ -141,10 +200,16 @@ #define CLKID_VCLK2_DIV4 192 #define CLKID_VCLK2_DIV6 193 #define CLKID_VCLK2_DIV12 194 +#define CLKID_CTS_ENCI_SEL 195 +#define CLKID_CTS_ENCP_SEL 196 +#define CLKID_CTS_VDAC_SEL 197 +#define CLKID_HDMI_TX_SEL 198 #define CLKID_CTS_ENCI 199 #define CLKID_CTS_ENCP 200 #define CLKID_CTS_VDAC 201 #define CLKID_HDMI_TX 202 +#define CLKID_HDMI_SEL 203 +#define CLKID_HDMI_DIV 204 #define CLKID_HDMI 205 #define CLKID_ACODEC 206 -- cgit v1.2.3 From 8fdbdc791873f37747cbcebab91aa8ad4aafa898 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:25 +0200 Subject: dt-bindings: clk: axg-clkc: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every axg-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-8-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.h | 58 ------------------------------------ include/dt-bindings/clock/axg-clkc.h | 48 +++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 58 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 39f9e2db82bd..ed157532b4d7 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -102,64 +102,6 @@ #define HHI_DPLL_TOP_I 0x318 #define HHI_DPLL_TOP2_I 0x31C -/* - * CLKID index values - * - * These indices are entirely contrived and do not map onto the hardware. - * It has now been decided to expose everything by default in the DT header: - * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want - * to expose, such as the internal muxes and dividers of composite clocks, - * will remain defined here. - */ -#define CLKID_MPEG_SEL 8 -#define CLKID_MPEG_DIV 9 -#define CLKID_SD_EMMC_B_CLK0_SEL 61 -#define CLKID_SD_EMMC_B_CLK0_DIV 62 -#define CLKID_SD_EMMC_C_CLK0_SEL 63 -#define CLKID_SD_EMMC_C_CLK0_DIV 64 -#define CLKID_MPLL0_DIV 65 -#define CLKID_MPLL1_DIV 66 -#define CLKID_MPLL2_DIV 67 -#define CLKID_MPLL3_DIV 68 -#define CLKID_MPLL_PREDIV 70 -#define CLKID_FCLK_DIV2_DIV 71 -#define CLKID_FCLK_DIV3_DIV 72 -#define CLKID_FCLK_DIV4_DIV 73 -#define CLKID_FCLK_DIV5_DIV 74 -#define CLKID_FCLK_DIV7_DIV 75 -#define CLKID_PCIE_PLL 76 -#define CLKID_PCIE_MUX 77 -#define CLKID_PCIE_REF 78 -#define CLKID_GEN_CLK_SEL 82 -#define CLKID_GEN_CLK_DIV 83 -#define CLKID_SYS_PLL_DCO 85 -#define CLKID_FIXED_PLL_DCO 86 -#define CLKID_GP0_PLL_DCO 87 -#define CLKID_HIFI_PLL_DCO 88 -#define CLKID_PCIE_PLL_DCO 89 -#define CLKID_PCIE_PLL_OD 90 -#define CLKID_VPU_0_DIV 91 -#define CLKID_VPU_1_DIV 94 -#define CLKID_VAPB_0_DIV 98 -#define CLKID_VAPB_1_DIV 101 -#define CLKID_VCLK_SEL 108 -#define CLKID_VCLK2_SEL 109 -#define CLKID_VCLK_INPUT 110 -#define CLKID_VCLK2_INPUT 111 -#define CLKID_VCLK_DIV 112 -#define CLKID_VCLK2_DIV 113 -#define CLKID_VCLK_DIV2_EN 114 -#define CLKID_VCLK_DIV4_EN 115 -#define CLKID_VCLK_DIV6_EN 116 -#define CLKID_VCLK_DIV12_EN 117 -#define CLKID_VCLK2_DIV2_EN 118 -#define CLKID_VCLK2_DIV4_EN 119 -#define CLKID_VCLK2_DIV6_EN 120 -#define CLKID_VCLK2_DIV12_EN 121 -#define CLKID_CTS_ENCL_SEL 132 -#define CLKID_VDIN_MEAS_SEL 134 -#define CLKID_VDIN_MEAS_DIV 135 - /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index 93752ea107e3..442162822b88 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -16,6 +16,8 @@ #define CLKID_FCLK_DIV5 5 #define CLKID_FCLK_DIV7 6 #define CLKID_GP0_PLL 7 +#define CLKID_MPEG_SEL 8 +#define CLKID_MPEG_DIV 9 #define CLKID_CLK81 10 #define CLKID_MPLL0 11 #define CLKID_MPLL1 12 @@ -67,23 +69,66 @@ #define CLKID_AO_I2C 58 #define CLKID_SD_EMMC_B_CLK0 59 #define CLKID_SD_EMMC_C_CLK0 60 +#define CLKID_SD_EMMC_B_CLK0_SEL 61 +#define CLKID_SD_EMMC_B_CLK0_DIV 62 +#define CLKID_SD_EMMC_C_CLK0_SEL 63 +#define CLKID_SD_EMMC_C_CLK0_DIV 64 +#define CLKID_MPLL0_DIV 65 +#define CLKID_MPLL1_DIV 66 +#define CLKID_MPLL2_DIV 67 +#define CLKID_MPLL3_DIV 68 #define CLKID_HIFI_PLL 69 +#define CLKID_MPLL_PREDIV 70 +#define CLKID_FCLK_DIV2_DIV 71 +#define CLKID_FCLK_DIV3_DIV 72 +#define CLKID_FCLK_DIV4_DIV 73 +#define CLKID_FCLK_DIV5_DIV 74 +#define CLKID_FCLK_DIV7_DIV 75 +#define CLKID_PCIE_PLL 76 +#define CLKID_PCIE_MUX 77 +#define CLKID_PCIE_REF 78 #define CLKID_PCIE_CML_EN0 79 #define CLKID_PCIE_CML_EN1 80 +#define CLKID_GEN_CLK_SEL 82 +#define CLKID_GEN_CLK_DIV 83 #define CLKID_GEN_CLK 84 +#define CLKID_SYS_PLL_DCO 85 +#define CLKID_FIXED_PLL_DCO 86 +#define CLKID_GP0_PLL_DCO 87 +#define CLKID_HIFI_PLL_DCO 88 +#define CLKID_PCIE_PLL_DCO 89 +#define CLKID_PCIE_PLL_OD 90 +#define CLKID_VPU_0_DIV 91 #define CLKID_VPU_0_SEL 92 #define CLKID_VPU_0 93 +#define CLKID_VPU_1_DIV 94 #define CLKID_VPU_1_SEL 95 #define CLKID_VPU_1 96 #define CLKID_VPU 97 +#define CLKID_VAPB_0_DIV 98 #define CLKID_VAPB_0_SEL 99 #define CLKID_VAPB_0 100 +#define CLKID_VAPB_1_DIV 101 #define CLKID_VAPB_1_SEL 102 #define CLKID_VAPB_1 103 #define CLKID_VAPB_SEL 104 #define CLKID_VAPB 105 #define CLKID_VCLK 106 #define CLKID_VCLK2 107 +#define CLKID_VCLK_SEL 108 +#define CLKID_VCLK2_SEL 109 +#define CLKID_VCLK_INPUT 110 +#define CLKID_VCLK2_INPUT 111 +#define CLKID_VCLK_DIV 112 +#define CLKID_VCLK2_DIV 113 +#define CLKID_VCLK_DIV2_EN 114 +#define CLKID_VCLK_DIV4_EN 115 +#define CLKID_VCLK_DIV6_EN 116 +#define CLKID_VCLK_DIV12_EN 117 +#define CLKID_VCLK2_DIV2_EN 118 +#define CLKID_VCLK2_DIV4_EN 119 +#define CLKID_VCLK2_DIV6_EN 120 +#define CLKID_VCLK2_DIV12_EN 121 #define CLKID_VCLK_DIV1 122 #define CLKID_VCLK_DIV2 123 #define CLKID_VCLK_DIV4 124 @@ -94,7 +139,10 @@ #define CLKID_VCLK2_DIV4 129 #define CLKID_VCLK2_DIV6 130 #define CLKID_VCLK2_DIV12 131 +#define CLKID_CTS_ENCL_SEL 132 #define CLKID_CTS_ENCL 133 +#define CLKID_VDIN_MEAS_SEL 134 +#define CLKID_VDIN_MEAS_DIV 135 #define CLKID_VDIN_MEAS 136 #endif /* __AXG_CLKC_H */ -- cgit v1.2.3 From b1262497a2e09dbeaa57e9fc4a4f949b53ce6323 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:26 +0200 Subject: dt-bindings: clk: g12a-clks: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every g12a-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-9-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet --- drivers/clk/meson/g12a.h | 140 ---------------------------------- include/dt-bindings/clock/g12a-clkc.h | 130 +++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+), 140 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index a70a0cba892b..8e08af3c1476 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -126,146 +126,6 @@ #define HHI_SYS1_PLL_CNTL5 0x394 #define HHI_SYS1_PLL_CNTL6 0x398 -/* - * CLKID index values - * - * These indices are entirely contrived and do not map onto the hardware. - * It has now been decided to expose everything by default in the DT header: - * include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want - * to expose, such as the internal muxes and dividers of composite clocks, - * will remain defined here. - */ -#define CLKID_MPEG_SEL 8 -#define CLKID_MPEG_DIV 9 -#define CLKID_SD_EMMC_A_CLK0_SEL 63 -#define CLKID_SD_EMMC_A_CLK0_DIV 64 -#define CLKID_SD_EMMC_B_CLK0_SEL 65 -#define CLKID_SD_EMMC_B_CLK0_DIV 66 -#define CLKID_SD_EMMC_C_CLK0_SEL 67 -#define CLKID_SD_EMMC_C_CLK0_DIV 68 -#define CLKID_MPLL0_DIV 69 -#define CLKID_MPLL1_DIV 70 -#define CLKID_MPLL2_DIV 71 -#define CLKID_MPLL3_DIV 72 -#define CLKID_MPLL_PREDIV 73 -#define CLKID_FCLK_DIV2_DIV 75 -#define CLKID_FCLK_DIV3_DIV 76 -#define CLKID_FCLK_DIV4_DIV 77 -#define CLKID_FCLK_DIV5_DIV 78 -#define CLKID_FCLK_DIV7_DIV 79 -#define CLKID_FCLK_DIV2P5_DIV 100 -#define CLKID_FIXED_PLL_DCO 101 -#define CLKID_SYS_PLL_DCO 102 -#define CLKID_GP0_PLL_DCO 103 -#define CLKID_HIFI_PLL_DCO 104 -#define CLKID_VPU_0_DIV 111 -#define CLKID_VPU_1_DIV 114 -#define CLKID_VAPB_0_DIV 118 -#define CLKID_VAPB_1_DIV 121 -#define CLKID_HDMI_PLL_DCO 125 -#define CLKID_HDMI_PLL_OD 126 -#define CLKID_HDMI_PLL_OD2 127 -#define CLKID_VID_PLL_SEL 130 -#define CLKID_VID_PLL_DIV 131 -#define CLKID_VCLK_SEL 132 -#define CLKID_VCLK2_SEL 133 -#define CLKID_VCLK_INPUT 134 -#define CLKID_VCLK2_INPUT 135 -#define CLKID_VCLK_DIV 136 -#define CLKID_VCLK2_DIV 137 -#define CLKID_VCLK_DIV2_EN 140 -#define CLKID_VCLK_DIV4_EN 141 -#define CLKID_VCLK_DIV6_EN 142 -#define CLKID_VCLK_DIV12_EN 143 -#define CLKID_VCLK2_DIV2_EN 144 -#define CLKID_VCLK2_DIV4_EN 145 -#define CLKID_VCLK2_DIV6_EN 146 -#define CLKID_VCLK2_DIV12_EN 147 -#define CLKID_CTS_ENCI_SEL 158 -#define CLKID_CTS_ENCP_SEL 159 -#define CLKID_CTS_VDAC_SEL 160 -#define CLKID_HDMI_TX_SEL 161 -#define CLKID_HDMI_SEL 166 -#define CLKID_HDMI_DIV 167 -#define CLKID_MALI_0_DIV 170 -#define CLKID_MALI_1_DIV 173 -#define CLKID_MPLL_50M_DIV 176 -#define CLKID_SYS_PLL_DIV16_EN 178 -#define CLKID_SYS_PLL_DIV16 179 -#define CLKID_CPU_CLK_DYN0_SEL 180 -#define CLKID_CPU_CLK_DYN0_DIV 181 -#define CLKID_CPU_CLK_DYN0 182 -#define CLKID_CPU_CLK_DYN1_SEL 183 -#define CLKID_CPU_CLK_DYN1_DIV 184 -#define CLKID_CPU_CLK_DYN1 185 -#define CLKID_CPU_CLK_DYN 186 -#define CLKID_CPU_CLK_DIV16_EN 188 -#define CLKID_CPU_CLK_DIV16 189 -#define CLKID_CPU_CLK_APB_DIV 190 -#define CLKID_CPU_CLK_APB 191 -#define CLKID_CPU_CLK_ATB_DIV 192 -#define CLKID_CPU_CLK_ATB 193 -#define CLKID_CPU_CLK_AXI_DIV 194 -#define CLKID_CPU_CLK_AXI 195 -#define CLKID_CPU_CLK_TRACE_DIV 196 -#define CLKID_CPU_CLK_TRACE 197 -#define CLKID_PCIE_PLL_DCO 198 -#define CLKID_PCIE_PLL_DCO_DIV2 199 -#define CLKID_PCIE_PLL_OD 200 -#define CLKID_VDEC_1_SEL 202 -#define CLKID_VDEC_1_DIV 203 -#define CLKID_VDEC_HEVC_SEL 205 -#define CLKID_VDEC_HEVC_DIV 206 -#define CLKID_VDEC_HEVCF_SEL 208 -#define CLKID_VDEC_HEVCF_DIV 209 -#define CLKID_TS_DIV 211 -#define CLKID_SYS1_PLL_DCO 213 -#define CLKID_SYS1_PLL 214 -#define CLKID_SYS1_PLL_DIV16_EN 215 -#define CLKID_SYS1_PLL_DIV16 216 -#define CLKID_CPUB_CLK_DYN0_SEL 217 -#define CLKID_CPUB_CLK_DYN0_DIV 218 -#define CLKID_CPUB_CLK_DYN0 219 -#define CLKID_CPUB_CLK_DYN1_SEL 220 -#define CLKID_CPUB_CLK_DYN1_DIV 221 -#define CLKID_CPUB_CLK_DYN1 222 -#define CLKID_CPUB_CLK_DYN 223 -#define CLKID_CPUB_CLK_DIV16_EN 225 -#define CLKID_CPUB_CLK_DIV16 226 -#define CLKID_CPUB_CLK_DIV2 227 -#define CLKID_CPUB_CLK_DIV3 228 -#define CLKID_CPUB_CLK_DIV4 229 -#define CLKID_CPUB_CLK_DIV5 230 -#define CLKID_CPUB_CLK_DIV6 231 -#define CLKID_CPUB_CLK_DIV7 232 -#define CLKID_CPUB_CLK_DIV8 233 -#define CLKID_CPUB_CLK_APB_SEL 234 -#define CLKID_CPUB_CLK_APB 235 -#define CLKID_CPUB_CLK_ATB_SEL 236 -#define CLKID_CPUB_CLK_ATB 237 -#define CLKID_CPUB_CLK_AXI_SEL 238 -#define CLKID_CPUB_CLK_AXI 239 -#define CLKID_CPUB_CLK_TRACE_SEL 240 -#define CLKID_CPUB_CLK_TRACE 241 -#define CLKID_GP1_PLL_DCO 242 -#define CLKID_DSU_CLK_DYN0_SEL 244 -#define CLKID_DSU_CLK_DYN0_DIV 245 -#define CLKID_DSU_CLK_DYN0 246 -#define CLKID_DSU_CLK_DYN1_SEL 247 -#define CLKID_DSU_CLK_DYN1_DIV 248 -#define CLKID_DSU_CLK_DYN1 249 -#define CLKID_DSU_CLK_DYN 250 -#define CLKID_DSU_CLK_FINAL 251 -#define CLKID_SPICC0_SCLK_SEL 256 -#define CLKID_SPICC0_SCLK_DIV 257 -#define CLKID_SPICC1_SCLK_SEL 259 -#define CLKID_SPICC1_SCLK_DIV 260 -#define CLKID_NNA_AXI_CLK_SEL 262 -#define CLKID_NNA_AXI_CLK_DIV 263 -#define CLKID_NNA_CORE_CLK_SEL 265 -#define CLKID_NNA_CORE_CLK_DIV 266 -#define CLKID_MIPI_DSI_PXCLK_DIV 268 - /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index a93b58c5e18e..387767f4e298 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -16,6 +16,8 @@ #define CLKID_FCLK_DIV5 5 #define CLKID_FCLK_DIV7 6 #define CLKID_GP0_PLL 7 +#define CLKID_MPEG_SEL 8 +#define CLKID_MPEG_DIV 9 #define CLKID_CLK81 10 #define CLKID_MPLL0 11 #define CLKID_MPLL1 12 @@ -69,7 +71,23 @@ #define CLKID_SD_EMMC_A_CLK0 60 #define CLKID_SD_EMMC_B_CLK0 61 #define CLKID_SD_EMMC_C_CLK0 62 +#define CLKID_SD_EMMC_A_CLK0_SEL 63 +#define CLKID_SD_EMMC_A_CLK0_DIV 64 +#define CLKID_SD_EMMC_B_CLK0_SEL 65 +#define CLKID_SD_EMMC_B_CLK0_DIV 66 +#define CLKID_SD_EMMC_C_CLK0_SEL 67 +#define CLKID_SD_EMMC_C_CLK0_DIV 68 +#define CLKID_MPLL0_DIV 69 +#define CLKID_MPLL1_DIV 70 +#define CLKID_MPLL2_DIV 71 +#define CLKID_MPLL3_DIV 72 +#define CLKID_MPLL_PREDIV 73 #define CLKID_HIFI_PLL 74 +#define CLKID_FCLK_DIV2_DIV 75 +#define CLKID_FCLK_DIV3_DIV 76 +#define CLKID_FCLK_DIV4_DIV 77 +#define CLKID_FCLK_DIV5_DIV 78 +#define CLKID_FCLK_DIV7_DIV 79 #define CLKID_VCLK2_VENCI0 80 #define CLKID_VCLK2_VENCI1 81 #define CLKID_VCLK2_VENCP0 82 @@ -90,26 +108,54 @@ #define CLKID_VCLK2_VENCL 97 #define CLKID_VCLK2_OTHER1 98 #define CLKID_FCLK_DIV2P5 99 +#define CLKID_FCLK_DIV2P5_DIV 100 +#define CLKID_FIXED_PLL_DCO 101 +#define CLKID_SYS_PLL_DCO 102 +#define CLKID_GP0_PLL_DCO 103 +#define CLKID_HIFI_PLL_DCO 104 #define CLKID_DMA 105 #define CLKID_EFUSE 106 #define CLKID_ROM_BOOT 107 #define CLKID_RESET_SEC 108 #define CLKID_SEC_AHB_APB3 109 #define CLKID_VPU_0_SEL 110 +#define CLKID_VPU_0_DIV 111 #define CLKID_VPU_0 112 #define CLKID_VPU_1_SEL 113 +#define CLKID_VPU_1_DIV 114 #define CLKID_VPU_1 115 #define CLKID_VPU 116 #define CLKID_VAPB_0_SEL 117 +#define CLKID_VAPB_0_DIV 118 #define CLKID_VAPB_0 119 #define CLKID_VAPB_1_SEL 120 +#define CLKID_VAPB_1_DIV 121 #define CLKID_VAPB_1 122 #define CLKID_VAPB_SEL 123 #define CLKID_VAPB 124 +#define CLKID_HDMI_PLL_DCO 125 +#define CLKID_HDMI_PLL_OD 126 +#define CLKID_HDMI_PLL_OD2 127 #define CLKID_HDMI_PLL 128 #define CLKID_VID_PLL 129 +#define CLKID_VID_PLL_SEL 130 +#define CLKID_VID_PLL_DIV 131 +#define CLKID_VCLK_SEL 132 +#define CLKID_VCLK2_SEL 133 +#define CLKID_VCLK_INPUT 134 +#define CLKID_VCLK2_INPUT 135 +#define CLKID_VCLK_DIV 136 +#define CLKID_VCLK2_DIV 137 #define CLKID_VCLK 138 #define CLKID_VCLK2 139 +#define CLKID_VCLK_DIV2_EN 140 +#define CLKID_VCLK_DIV4_EN 141 +#define CLKID_VCLK_DIV6_EN 142 +#define CLKID_VCLK_DIV12_EN 143 +#define CLKID_VCLK2_DIV2_EN 144 +#define CLKID_VCLK2_DIV4_EN 145 +#define CLKID_VCLK2_DIV6_EN 146 +#define CLKID_VCLK2_DIV12_EN 147 #define CLKID_VCLK_DIV1 148 #define CLKID_VCLK_DIV2 149 #define CLKID_VCLK_DIV4 150 @@ -120,33 +166,117 @@ #define CLKID_VCLK2_DIV4 155 #define CLKID_VCLK2_DIV6 156 #define CLKID_VCLK2_DIV12 157 +#define CLKID_CTS_ENCI_SEL 158 +#define CLKID_CTS_ENCP_SEL 159 +#define CLKID_CTS_VDAC_SEL 160 +#define CLKID_HDMI_TX_SEL 161 #define CLKID_CTS_ENCI 162 #define CLKID_CTS_ENCP 163 #define CLKID_CTS_VDAC 164 #define CLKID_HDMI_TX 165 +#define CLKID_HDMI_SEL 166 +#define CLKID_HDMI_DIV 167 #define CLKID_HDMI 168 #define CLKID_MALI_0_SEL 169 +#define CLKID_MALI_0_DIV 170 #define CLKID_MALI_0 171 #define CLKID_MALI_1_SEL 172 +#define CLKID_MALI_1_DIV 173 #define CLKID_MALI_1 174 #define CLKID_MALI 175 +#define CLKID_MPLL_50M_DIV 176 #define CLKID_MPLL_50M 177 +#define CLKID_SYS_PLL_DIV16_EN 178 +#define CLKID_SYS_PLL_DIV16 179 +#define CLKID_CPU_CLK_DYN0_SEL 180 +#define CLKID_CPU_CLK_DYN0_DIV 181 +#define CLKID_CPU_CLK_DYN0 182 +#define CLKID_CPU_CLK_DYN1_SEL 183 +#define CLKID_CPU_CLK_DYN1_DIV 184 +#define CLKID_CPU_CLK_DYN1 185 +#define CLKID_CPU_CLK_DYN 186 #define CLKID_CPU_CLK 187 +#define CLKID_CPU_CLK_DIV16_EN 188 +#define CLKID_CPU_CLK_DIV16 189 +#define CLKID_CPU_CLK_APB_DIV 190 +#define CLKID_CPU_CLK_APB 191 +#define CLKID_CPU_CLK_ATB_DIV 192 +#define CLKID_CPU_CLK_ATB 193 +#define CLKID_CPU_CLK_AXI_DIV 194 +#define CLKID_CPU_CLK_AXI 195 +#define CLKID_CPU_CLK_TRACE_DIV 196 +#define CLKID_CPU_CLK_TRACE 197 +#define CLKID_PCIE_PLL_DCO 198 +#define CLKID_PCIE_PLL_DCO_DIV2 199 +#define CLKID_PCIE_PLL_OD 200 #define CLKID_PCIE_PLL 201 +#define CLKID_VDEC_1_SEL 202 +#define CLKID_VDEC_1_DIV 203 #define CLKID_VDEC_1 204 +#define CLKID_VDEC_HEVC_SEL 205 +#define CLKID_VDEC_HEVC_DIV 206 #define CLKID_VDEC_HEVC 207 +#define CLKID_VDEC_HEVCF_SEL 208 +#define CLKID_VDEC_HEVCF_DIV 209 #define CLKID_VDEC_HEVCF 210 +#define CLKID_TS_DIV 211 #define CLKID_TS 212 +#define CLKID_SYS1_PLL_DCO 213 +#define CLKID_SYS1_PLL 214 +#define CLKID_SYS1_PLL_DIV16_EN 215 +#define CLKID_SYS1_PLL_DIV16 216 +#define CLKID_CPUB_CLK_DYN0_SEL 217 +#define CLKID_CPUB_CLK_DYN0_DIV 218 +#define CLKID_CPUB_CLK_DYN0 219 +#define CLKID_CPUB_CLK_DYN1_SEL 220 +#define CLKID_CPUB_CLK_DYN1_DIV 221 +#define CLKID_CPUB_CLK_DYN1 222 +#define CLKID_CPUB_CLK_DYN 223 #define CLKID_CPUB_CLK 224 +#define CLKID_CPUB_CLK_DIV16_EN 225 +#define CLKID_CPUB_CLK_DIV16 226 +#define CLKID_CPUB_CLK_DIV2 227 +#define CLKID_CPUB_CLK_DIV3 228 +#define CLKID_CPUB_CLK_DIV4 229 +#define CLKID_CPUB_CLK_DIV5 230 +#define CLKID_CPUB_CLK_DIV6 231 +#define CLKID_CPUB_CLK_DIV7 232 +#define CLKID_CPUB_CLK_DIV8 233 +#define CLKID_CPUB_CLK_APB_SEL 234 +#define CLKID_CPUB_CLK_APB 235 +#define CLKID_CPUB_CLK_ATB_SEL 236 +#define CLKID_CPUB_CLK_ATB 237 +#define CLKID_CPUB_CLK_AXI_SEL 238 +#define CLKID_CPUB_CLK_AXI 239 +#define CLKID_CPUB_CLK_TRACE_SEL 240 +#define CLKID_CPUB_CLK_TRACE 241 +#define CLKID_GP1_PLL_DCO 242 #define CLKID_GP1_PLL 243 +#define CLKID_DSU_CLK_DYN0_SEL 244 +#define CLKID_DSU_CLK_DYN0_DIV 245 +#define CLKID_DSU_CLK_DYN0 246 +#define CLKID_DSU_CLK_DYN1_SEL 247 +#define CLKID_DSU_CLK_DYN1_DIV 248 +#define CLKID_DSU_CLK_DYN1 249 +#define CLKID_DSU_CLK_DYN 250 +#define CLKID_DSU_CLK_FINAL 251 #define CLKID_DSU_CLK 252 #define CLKID_CPU1_CLK 253 #define CLKID_CPU2_CLK 254 #define CLKID_CPU3_CLK 255 +#define CLKID_SPICC0_SCLK_SEL 256 +#define CLKID_SPICC0_SCLK_DIV 257 #define CLKID_SPICC0_SCLK 258 +#define CLKID_SPICC1_SCLK_SEL 259 +#define CLKID_SPICC1_SCLK_DIV 260 #define CLKID_SPICC1_SCLK 261 +#define CLKID_NNA_AXI_CLK_SEL 262 +#define CLKID_NNA_AXI_CLK_DIV 263 #define CLKID_NNA_AXI_CLK 264 +#define CLKID_NNA_CORE_CLK_SEL 265 +#define CLKID_NNA_CORE_CLK_DIV 266 #define CLKID_NNA_CORE_CLK 267 +#define CLKID_MIPI_DSI_PXCLK_DIV 268 #define CLKID_MIPI_DSI_PXCLK_SEL 269 #define CLKID_MIPI_DSI_PXCLK 270 -- cgit v1.2.3 From 6655744d9a15142f32d6e2bd24fcaa13cb24174f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:27 +0200 Subject: dt-bindings: clk: g12a-aoclkc: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every g12a-aoclkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-10-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet --- drivers/clk/meson/g12a-aoclk.h | 17 ----------------- include/dt-bindings/clock/g12a-aoclkc.h | 7 +++++++ 2 files changed, 7 insertions(+), 17 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/meson/g12a-aoclk.h b/drivers/clk/meson/g12a-aoclk.h index 077bd25b94a1..9d6eeb24ae0c 100644 --- a/drivers/clk/meson/g12a-aoclk.h +++ b/drivers/clk/meson/g12a-aoclk.h @@ -7,23 +7,6 @@ #ifndef __G12A_AOCLKC_H #define __G12A_AOCLKC_H -/* - * CLKID index values - * - * These indices are entirely contrived and do not map onto the hardware. - * It has now been decided to expose everything by default in the DT header: - * include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want - * to expose, such as the internal muxes and dividers of composite clocks, - * will remain defined here. - */ -#define CLKID_AO_SAR_ADC_DIV 17 -#define CLKID_AO_32K_PRE 20 -#define CLKID_AO_32K_DIV 21 -#define CLKID_AO_32K_SEL 22 -#define CLKID_AO_CEC_PRE 24 -#define CLKID_AO_CEC_DIV 25 -#define CLKID_AO_CEC_SEL 26 - #include #include diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h index e916e49ff288..8fe7712fb12d 100644 --- a/include/dt-bindings/clock/g12a-aoclkc.h +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -26,10 +26,17 @@ #define CLKID_AO_M4_FCLK 13 #define CLKID_AO_M4_HCLK 14 #define CLKID_AO_CLK81 15 +#define CLKID_AO_SAR_ADC_DIV 17 #define CLKID_AO_SAR_ADC_SEL 16 #define CLKID_AO_SAR_ADC_CLK 18 #define CLKID_AO_CTS_OSCIN 19 +#define CLKID_AO_32K_PRE 20 +#define CLKID_AO_32K_DIV 21 +#define CLKID_AO_32K_SEL 22 #define CLKID_AO_32K 23 +#define CLKID_AO_CEC_PRE 24 +#define CLKID_AO_CEC_DIV 25 +#define CLKID_AO_CEC_SEL 26 #define CLKID_AO_CEC 27 #define CLKID_AO_CTS_RTC_OSCIN 28 -- cgit v1.2.3 From 165a1941959b2e4ceadd8da959eaa320d11edd58 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:28 +0200 Subject: dt-bindings: clk: meson8b-clkc: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every meson8b-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-11-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8b.h | 108 ------------------------------- include/dt-bindings/clock/meson8b-clkc.h | 97 +++++++++++++++++++++++++++ 2 files changed, 97 insertions(+), 108 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index f999655d4436..2a9c4fe29ca2 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -77,114 +77,6 @@ #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ -/* - * CLKID index values - * - * These indices are entirely contrived and do not map onto the hardware. - * It has now been decided to expose everything by default in the DT header: - * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want - * to expose, such as the internal muxes and dividers of composite clocks, - * will remain defined here. - */ - -#define CLKID_MPLL0_DIV 96 -#define CLKID_MPLL1_DIV 97 -#define CLKID_MPLL2_DIV 98 -#define CLKID_CPU_IN_SEL 99 -#define CLKID_CPU_IN_DIV2 100 -#define CLKID_CPU_IN_DIV3 101 -#define CLKID_CPU_SCALE_DIV 102 -#define CLKID_CPU_SCALE_OUT_SEL 103 -#define CLKID_MPLL_PREDIV 104 -#define CLKID_FCLK_DIV2_DIV 105 -#define CLKID_FCLK_DIV3_DIV 106 -#define CLKID_FCLK_DIV4_DIV 107 -#define CLKID_FCLK_DIV5_DIV 108 -#define CLKID_FCLK_DIV7_DIV 109 -#define CLKID_NAND_SEL 110 -#define CLKID_NAND_DIV 111 -#define CLKID_PLL_FIXED_DCO 113 -#define CLKID_HDMI_PLL_DCO 114 -#define CLKID_PLL_SYS_DCO 115 -#define CLKID_CPU_CLK_DIV2 116 -#define CLKID_CPU_CLK_DIV3 117 -#define CLKID_CPU_CLK_DIV4 118 -#define CLKID_CPU_CLK_DIV5 119 -#define CLKID_CPU_CLK_DIV6 120 -#define CLKID_CPU_CLK_DIV7 121 -#define CLKID_CPU_CLK_DIV8 122 -#define CLKID_APB_SEL 123 -#define CLKID_PERIPH_SEL 125 -#define CLKID_AXI_SEL 127 -#define CLKID_L2_DRAM_SEL 129 -#define CLKID_HDMI_PLL_LVDS_OUT 131 -#define CLKID_VID_PLL_IN_SEL 133 -#define CLKID_VID_PLL_IN_EN 134 -#define CLKID_VID_PLL_PRE_DIV 135 -#define CLKID_VID_PLL_POST_DIV 136 -#define CLKID_VCLK_IN_EN 139 -#define CLKID_VCLK_DIV1 140 -#define CLKID_VCLK_DIV2_DIV 141 -#define CLKID_VCLK_DIV2 142 -#define CLKID_VCLK_DIV4_DIV 143 -#define CLKID_VCLK_DIV4 144 -#define CLKID_VCLK_DIV6_DIV 145 -#define CLKID_VCLK_DIV6 146 -#define CLKID_VCLK_DIV12_DIV 147 -#define CLKID_VCLK_DIV12 148 -#define CLKID_VCLK2_IN_EN 150 -#define CLKID_VCLK2_DIV1 151 -#define CLKID_VCLK2_DIV2_DIV 152 -#define CLKID_VCLK2_DIV2 153 -#define CLKID_VCLK2_DIV4_DIV 154 -#define CLKID_VCLK2_DIV4 155 -#define CLKID_VCLK2_DIV6_DIV 156 -#define CLKID_VCLK2_DIV6 157 -#define CLKID_VCLK2_DIV12_DIV 158 -#define CLKID_VCLK2_DIV12 159 -#define CLKID_CTS_ENCT_SEL 160 -#define CLKID_CTS_ENCP_SEL 162 -#define CLKID_CTS_ENCI_SEL 164 -#define CLKID_HDMI_TX_PIXEL_SEL 166 -#define CLKID_CTS_ENCL_SEL 168 -#define CLKID_CTS_VDAC0_SEL 170 -#define CLKID_HDMI_SYS_SEL 172 -#define CLKID_HDMI_SYS_DIV 173 -#define CLKID_MALI_0_SEL 175 -#define CLKID_MALI_0_DIV 176 -#define CLKID_MALI_0 177 -#define CLKID_MALI_1_SEL 178 -#define CLKID_MALI_1_DIV 179 -#define CLKID_MALI_1 180 -#define CLKID_GP_PLL_DCO 181 -#define CLKID_GP_PLL 182 -#define CLKID_VPU_0_SEL 183 -#define CLKID_VPU_0_DIV 184 -#define CLKID_VPU_0 185 -#define CLKID_VPU_1_SEL 186 -#define CLKID_VPU_1_DIV 187 -#define CLKID_VPU_1 189 -#define CLKID_VDEC_1_SEL 191 -#define CLKID_VDEC_1_1_DIV 192 -#define CLKID_VDEC_1_1 193 -#define CLKID_VDEC_1_2_DIV 194 -#define CLKID_VDEC_1_2 195 -#define CLKID_VDEC_HCODEC_SEL 197 -#define CLKID_VDEC_HCODEC_DIV 198 -#define CLKID_VDEC_2_SEL 200 -#define CLKID_VDEC_2_DIV 201 -#define CLKID_VDEC_HEVC_SEL 203 -#define CLKID_VDEC_HEVC_DIV 204 -#define CLKID_VDEC_HEVC_EN 205 -#define CLKID_CTS_AMCLK_SEL 207 -#define CLKID_CTS_AMCLK_DIV 208 -#define CLKID_CTS_MCLK_I958_SEL 210 -#define CLKID_CTS_MCLK_I958_DIV 211 -#define CLKID_VCLK_EN 214 -#define CLKID_VCLK2_EN 215 -#define CLKID_VID_PLL_LVDS_EN 216 -#define CLKID_HDMI_PLL_DCO_IN 217 - /* * include the CLKID and RESETID that have * been made part of the stable DT binding diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 78aa07fd7cc0..385bf243c56c 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -100,29 +100,126 @@ #define CLKID_MPLL0 93 #define CLKID_MPLL1 94 #define CLKID_MPLL2 95 +#define CLKID_MPLL0_DIV 96 +#define CLKID_MPLL1_DIV 97 +#define CLKID_MPLL2_DIV 98 +#define CLKID_CPU_IN_SEL 99 +#define CLKID_CPU_IN_DIV2 100 +#define CLKID_CPU_IN_DIV3 101 +#define CLKID_CPU_SCALE_DIV 102 +#define CLKID_CPU_SCALE_OUT_SEL 103 +#define CLKID_MPLL_PREDIV 104 +#define CLKID_FCLK_DIV2_DIV 105 +#define CLKID_FCLK_DIV3_DIV 106 +#define CLKID_FCLK_DIV4_DIV 107 +#define CLKID_FCLK_DIV5_DIV 108 +#define CLKID_FCLK_DIV7_DIV 109 +#define CLKID_NAND_SEL 110 +#define CLKID_NAND_DIV 111 #define CLKID_NAND_CLK 112 +#define CLKID_PLL_FIXED_DCO 113 +#define CLKID_HDMI_PLL_DCO 114 +#define CLKID_PLL_SYS_DCO 115 +#define CLKID_CPU_CLK_DIV2 116 +#define CLKID_CPU_CLK_DIV3 117 +#define CLKID_CPU_CLK_DIV4 118 +#define CLKID_CPU_CLK_DIV5 119 +#define CLKID_CPU_CLK_DIV6 120 +#define CLKID_CPU_CLK_DIV7 121 +#define CLKID_CPU_CLK_DIV8 122 +#define CLKID_APB_SEL 123 #define CLKID_APB 124 +#define CLKID_PERIPH_SEL 125 #define CLKID_PERIPH 126 +#define CLKID_AXI_SEL 127 #define CLKID_AXI 128 #define CLKID_L2_DRAM 130 +#define CLKID_L2_DRAM_SEL 129 +#define CLKID_HDMI_PLL_LVDS_OUT 131 #define CLKID_HDMI_PLL_HDMI_OUT 132 +#define CLKID_VID_PLL_IN_SEL 133 +#define CLKID_VID_PLL_IN_EN 134 +#define CLKID_VID_PLL_PRE_DIV 135 +#define CLKID_VID_PLL_POST_DIV 136 #define CLKID_VID_PLL_FINAL_DIV 137 #define CLKID_VCLK_IN_SEL 138 +#define CLKID_VCLK_IN_EN 139 +#define CLKID_VCLK_DIV1 140 +#define CLKID_VCLK_DIV2_DIV 141 +#define CLKID_VCLK_DIV2 142 +#define CLKID_VCLK_DIV4_DIV 143 +#define CLKID_VCLK_DIV4 144 +#define CLKID_VCLK_DIV6_DIV 145 +#define CLKID_VCLK_DIV6 146 +#define CLKID_VCLK_DIV12_DIV 147 +#define CLKID_VCLK_DIV12 148 #define CLKID_VCLK2_IN_SEL 149 +#define CLKID_VCLK2_IN_EN 150 +#define CLKID_VCLK2_DIV1 151 +#define CLKID_VCLK2_DIV2_DIV 152 +#define CLKID_VCLK2_DIV2 153 +#define CLKID_VCLK2_DIV4_DIV 154 +#define CLKID_VCLK2_DIV4 155 +#define CLKID_VCLK2_DIV6_DIV 156 +#define CLKID_VCLK2_DIV6 157 +#define CLKID_VCLK2_DIV12_DIV 158 +#define CLKID_VCLK2_DIV12 159 +#define CLKID_CTS_ENCT_SEL 160 #define CLKID_CTS_ENCT 161 +#define CLKID_CTS_ENCP_SEL 162 #define CLKID_CTS_ENCP 163 +#define CLKID_CTS_ENCI_SEL 164 #define CLKID_CTS_ENCI 165 +#define CLKID_HDMI_TX_PIXEL_SEL 166 #define CLKID_HDMI_TX_PIXEL 167 +#define CLKID_CTS_ENCL_SEL 168 #define CLKID_CTS_ENCL 169 +#define CLKID_CTS_VDAC0_SEL 170 #define CLKID_CTS_VDAC0 171 +#define CLKID_HDMI_SYS_SEL 172 +#define CLKID_HDMI_SYS_DIV 173 #define CLKID_HDMI_SYS 174 +#define CLKID_MALI_0_SEL 175 +#define CLKID_MALI_0_DIV 176 +#define CLKID_MALI_0 177 +#define CLKID_MALI_1_SEL 178 +#define CLKID_MALI_1_DIV 179 +#define CLKID_MALI_1 180 +#define CLKID_GP_PLL_DCO 181 +#define CLKID_GP_PLL 182 +#define CLKID_VPU_0_SEL 183 +#define CLKID_VPU_0_DIV 184 +#define CLKID_VPU_0 185 +#define CLKID_VPU_1_SEL 186 +#define CLKID_VPU_1_DIV 187 +#define CLKID_VPU_1 189 #define CLKID_VPU 190 +#define CLKID_VDEC_1_SEL 191 +#define CLKID_VDEC_1_1_DIV 192 +#define CLKID_VDEC_1_1 193 +#define CLKID_VDEC_1_2_DIV 194 +#define CLKID_VDEC_1_2 195 #define CLKID_VDEC_1 196 +#define CLKID_VDEC_HCODEC_SEL 197 +#define CLKID_VDEC_HCODEC_DIV 198 #define CLKID_VDEC_HCODEC 199 +#define CLKID_VDEC_2_SEL 200 +#define CLKID_VDEC_2_DIV 201 #define CLKID_VDEC_2 202 +#define CLKID_VDEC_HEVC_SEL 203 +#define CLKID_VDEC_HEVC_DIV 204 +#define CLKID_VDEC_HEVC_EN 205 #define CLKID_VDEC_HEVC 206 +#define CLKID_CTS_AMCLK_SEL 207 +#define CLKID_CTS_AMCLK_DIV 208 #define CLKID_CTS_AMCLK 209 +#define CLKID_CTS_MCLK_I958_SEL 210 +#define CLKID_CTS_MCLK_I958_DIV 211 #define CLKID_CTS_MCLK_I958 212 #define CLKID_CTS_I958 213 +#define CLKID_VCLK_EN 214 +#define CLKID_VCLK2_EN 215 +#define CLKID_VID_PLL_LVDS_EN 216 +#define CLKID_HDMI_PLL_DCO_IN 217 #endif /* __MESON8B_CLKC_H */ -- cgit v1.2.3 From 57049a1cfceaedb16e2b605c346b9d96b84ff1b9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:29 +0200 Subject: dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 peripherals ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Reviewed-by: Dmitry Rokosov Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-12-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet --- drivers/clk/meson/a1-peripherals.h | 63 ---------------------- .../clock/amlogic,a1-peripherals-clkc.h | 53 ++++++++++++++++++ 2 files changed, 53 insertions(+), 63 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peripherals.h index 4d60456a95a9..842b52634ed0 100644 --- a/drivers/clk/meson/a1-peripherals.h +++ b/drivers/clk/meson/a1-peripherals.h @@ -46,67 +46,4 @@ /* include the CLKIDs that have been made part of the DT binding */ #include -/* - * CLKID index values for internal clocks - * - * These indices are entirely contrived and do not map onto the hardware. - * It has now been decided to expose everything by default in the DT header: - * include/dt-bindings/clock/a1-peripherals-clkc.h. - * Only the clocks ids we don't want to expose, such as the internal muxes and - * dividers of composite clocks, will remain defined here. - */ -#define CLKID_XTAL_IN 0 -#define CLKID_DSPA_SEL 61 -#define CLKID_DSPB_SEL 62 -#define CLKID_SARADC_SEL 74 -#define CLKID_SYS_A_SEL 89 -#define CLKID_SYS_A_DIV 90 -#define CLKID_SYS_A 91 -#define CLKID_SYS_B_SEL 92 -#define CLKID_SYS_B_DIV 93 -#define CLKID_SYS_B 94 -#define CLKID_DSPA_A_DIV 96 -#define CLKID_DSPA_A 97 -#define CLKID_DSPA_B_DIV 99 -#define CLKID_DSPA_B 100 -#define CLKID_DSPB_A_DIV 102 -#define CLKID_DSPB_A 103 -#define CLKID_DSPB_B_DIV 105 -#define CLKID_DSPB_B 106 -#define CLKID_RTC_32K_IN 107 -#define CLKID_RTC_32K_DIV 108 -#define CLKID_RTC_32K_XTAL 109 -#define CLKID_RTC_32K_SEL 110 -#define CLKID_CECB_32K_IN 111 -#define CLKID_CECB_32K_DIV 112 -#define CLKID_CECA_32K_IN 115 -#define CLKID_CECA_32K_DIV 116 -#define CLKID_DIV2_PRE 119 -#define CLKID_24M_DIV2 120 -#define CLKID_GEN_DIV 122 -#define CLKID_SARADC_DIV 123 -#define CLKID_PWM_A_DIV 125 -#define CLKID_PWM_B_DIV 127 -#define CLKID_PWM_C_DIV 129 -#define CLKID_PWM_D_DIV 131 -#define CLKID_PWM_E_DIV 133 -#define CLKID_PWM_F_DIV 135 -#define CLKID_SPICC_SEL 136 -#define CLKID_SPICC_DIV 137 -#define CLKID_SPICC_SEL2 138 -#define CLKID_TS_DIV 139 -#define CLKID_SPIFC_SEL 140 -#define CLKID_SPIFC_DIV 141 -#define CLKID_SPIFC_SEL2 142 -#define CLKID_USB_BUS_SEL 143 -#define CLKID_USB_BUS_DIV 144 -#define CLKID_SD_EMMC_SEL 145 -#define CLKID_SD_EMMC_DIV 146 -#define CLKID_PSRAM_SEL 148 -#define CLKID_PSRAM_DIV 149 -#define CLKID_PSRAM_SEL2 150 -#define CLKID_DMC_SEL 151 -#define CLKID_DMC_DIV 152 -#define CLKID_DMC_SEL2 153 - #endif /* __A1_PERIPHERALS_H */ diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h index ff2730f398a6..06f198ee7623 100644 --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h @@ -10,6 +10,7 @@ #ifndef __A1_PERIPHERALS_CLKC_H #define __A1_PERIPHERALS_CLKC_H +#define CLKID_XTAL_IN 0 #define CLKID_FIXPLL_IN 1 #define CLKID_USB_PHY_IN 2 #define CLKID_USB_CTRL_IN 3 @@ -70,6 +71,8 @@ #define CLKID_CPU_CTRL 58 #define CLKID_ROM 59 #define CLKID_PROC_I2C 60 +#define CLKID_DSPA_SEL 61 +#define CLKID_DSPB_SEL 62 #define CLKID_DSPA_EN 63 #define CLKID_DSPA_EN_NIC 64 #define CLKID_DSPB_EN 65 @@ -81,6 +84,7 @@ #define CLKID_12M 71 #define CLKID_FCLK_DIV2_DIVN 72 #define CLKID_GEN 73 +#define CLKID_SARADC_SEL 74 #define CLKID_SARADC 75 #define CLKID_PWM_A 76 #define CLKID_PWM_B 77 @@ -95,21 +99,70 @@ #define CLKID_SD_EMMC 86 #define CLKID_PSRAM 87 #define CLKID_DMC 88 +#define CLKID_SYS_A_SEL 89 +#define CLKID_SYS_A_DIV 90 +#define CLKID_SYS_A 91 +#define CLKID_SYS_B_SEL 92 +#define CLKID_SYS_B_DIV 93 +#define CLKID_SYS_B 94 #define CLKID_DSPA_A_SEL 95 +#define CLKID_DSPA_A_DIV 96 +#define CLKID_DSPA_A 97 #define CLKID_DSPA_B_SEL 98 +#define CLKID_DSPA_B_DIV 99 +#define CLKID_DSPA_B 100 #define CLKID_DSPB_A_SEL 101 +#define CLKID_DSPB_A_DIV 102 +#define CLKID_DSPB_A 103 #define CLKID_DSPB_B_SEL 104 +#define CLKID_DSPB_B_DIV 105 +#define CLKID_DSPB_B 106 +#define CLKID_RTC_32K_IN 107 +#define CLKID_RTC_32K_DIV 108 +#define CLKID_RTC_32K_XTAL 109 +#define CLKID_RTC_32K_SEL 110 +#define CLKID_CECB_32K_IN 111 +#define CLKID_CECB_32K_DIV 112 #define CLKID_CECB_32K_SEL_PRE 113 #define CLKID_CECB_32K_SEL 114 +#define CLKID_CECA_32K_IN 115 +#define CLKID_CECA_32K_DIV 116 #define CLKID_CECA_32K_SEL_PRE 117 #define CLKID_CECA_32K_SEL 118 +#define CLKID_DIV2_PRE 119 +#define CLKID_24M_DIV2 120 #define CLKID_GEN_SEL 121 +#define CLKID_GEN_DIV 122 +#define CLKID_SARADC_DIV 123 #define CLKID_PWM_A_SEL 124 +#define CLKID_PWM_A_DIV 125 #define CLKID_PWM_B_SEL 126 +#define CLKID_PWM_B_DIV 127 #define CLKID_PWM_C_SEL 128 +#define CLKID_PWM_C_DIV 129 #define CLKID_PWM_D_SEL 130 +#define CLKID_PWM_D_DIV 131 #define CLKID_PWM_E_SEL 132 +#define CLKID_PWM_E_DIV 133 #define CLKID_PWM_F_SEL 134 +#define CLKID_PWM_F_DIV 135 +#define CLKID_SPICC_SEL 136 +#define CLKID_SPICC_DIV 137 +#define CLKID_SPICC_SEL2 138 +#define CLKID_TS_DIV 139 +#define CLKID_SPIFC_SEL 140 +#define CLKID_SPIFC_DIV 141 +#define CLKID_SPIFC_SEL2 142 +#define CLKID_USB_BUS_SEL 143 +#define CLKID_USB_BUS_DIV 144 +#define CLKID_SD_EMMC_SEL 145 +#define CLKID_SD_EMMC_DIV 146 #define CLKID_SD_EMMC_SEL2 147 +#define CLKID_PSRAM_SEL 148 +#define CLKID_PSRAM_DIV 149 +#define CLKID_PSRAM_SEL2 150 +#define CLKID_DMC_SEL 151 +#define CLKID_DMC_DIV 152 +#define CLKID_DMC_SEL2 153 #endif /* __A1_PERIPHERALS_CLKC_H */ -- cgit v1.2.3 From 09d65c026774e50357c8fd5ae7a7eb072723208c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:30 +0200 Subject: dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 pll ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Reviewed-by: Dmitry Rokosov Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-13-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet --- drivers/clk/meson/a1-pll.h | 15 --------------- include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 5 +++++ 2 files changed, 5 insertions(+), 15 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h index 82570759e6a2..0add1c7ea9f5 100644 --- a/drivers/clk/meson/a1-pll.h +++ b/drivers/clk/meson/a1-pll.h @@ -28,19 +28,4 @@ /* include the CLKIDs that have been made part of the DT binding */ #include -/* - * CLKID index values for internal clocks - * - * These indices are entirely contrived and do not map onto the hardware. - * It has now been decided to expose everything by default in the DT header: - * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want - * to expose, such as the internal muxes and dividers of composite clocks, - * will remain defined here. - */ -#define CLKID_FIXED_PLL_DCO 0 -#define CLKID_FCLK_DIV2_DIV 2 -#define CLKID_FCLK_DIV3_DIV 3 -#define CLKID_FCLK_DIV5_DIV 4 -#define CLKID_FCLK_DIV7_DIV 5 - #endif /* __A1_PLL_H */ diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h index 01fb8164ac29..2b660c0f2c9f 100644 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h @@ -10,7 +10,12 @@ #ifndef __A1_PLL_CLKC_H #define __A1_PLL_CLKC_H +#define CLKID_FIXED_PLL_DCO 0 #define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2_DIV 2 +#define CLKID_FCLK_DIV3_DIV 3 +#define CLKID_FCLK_DIV5_DIV 4 +#define CLKID_FCLK_DIV7_DIV 5 #define CLKID_FCLK_DIV2 6 #define CLKID_FCLK_DIV3 7 #define CLKID_FCLK_DIV5 8 -- cgit v1.2.3 From 40fb6772859cb18b62ae879d8815f271f22513b7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:31 +0200 Subject: dt-bindings: clk: axg-audio-clkc: expose all clock ids Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every axg-audio-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-14-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-audio.h | 70 ------------------------------ include/dt-bindings/clock/axg-audio-clkc.h | 65 +++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 70 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h index d6ed27c77729..faf08748b205 100644 --- a/drivers/clk/meson/axg-audio.h +++ b/drivers/clk/meson/axg-audio.h @@ -64,76 +64,6 @@ #define AUDIO_SM1_SW_RESET1 0x02C #define AUDIO_CLK81_CTRL 0x030 #define AUDIO_CLK81_EN 0x034 -/* - * CLKID index values - * These indices are entirely contrived and do not map onto the hardware. - */ - -#define AUD_CLKID_MST_A_MCLK_SEL 59 -#define AUD_CLKID_MST_B_MCLK_SEL 60 -#define AUD_CLKID_MST_C_MCLK_SEL 61 -#define AUD_CLKID_MST_D_MCLK_SEL 62 -#define AUD_CLKID_MST_E_MCLK_SEL 63 -#define AUD_CLKID_MST_F_MCLK_SEL 64 -#define AUD_CLKID_MST_A_MCLK_DIV 65 -#define AUD_CLKID_MST_B_MCLK_DIV 66 -#define AUD_CLKID_MST_C_MCLK_DIV 67 -#define AUD_CLKID_MST_D_MCLK_DIV 68 -#define AUD_CLKID_MST_E_MCLK_DIV 69 -#define AUD_CLKID_MST_F_MCLK_DIV 70 -#define AUD_CLKID_SPDIFOUT_CLK_SEL 71 -#define AUD_CLKID_SPDIFOUT_CLK_DIV 72 -#define AUD_CLKID_SPDIFIN_CLK_SEL 73 -#define AUD_CLKID_SPDIFIN_CLK_DIV 74 -#define AUD_CLKID_PDM_DCLK_SEL 75 -#define AUD_CLKID_PDM_DCLK_DIV 76 -#define AUD_CLKID_PDM_SYSCLK_SEL 77 -#define AUD_CLKID_PDM_SYSCLK_DIV 78 -#define AUD_CLKID_MST_A_SCLK_PRE_EN 92 -#define AUD_CLKID_MST_B_SCLK_PRE_EN 93 -#define AUD_CLKID_MST_C_SCLK_PRE_EN 94 -#define AUD_CLKID_MST_D_SCLK_PRE_EN 95 -#define AUD_CLKID_MST_E_SCLK_PRE_EN 96 -#define AUD_CLKID_MST_F_SCLK_PRE_EN 97 -#define AUD_CLKID_MST_A_SCLK_DIV 98 -#define AUD_CLKID_MST_B_SCLK_DIV 99 -#define AUD_CLKID_MST_C_SCLK_DIV 100 -#define AUD_CLKID_MST_D_SCLK_DIV 101 -#define AUD_CLKID_MST_E_SCLK_DIV 102 -#define AUD_CLKID_MST_F_SCLK_DIV 103 -#define AUD_CLKID_MST_A_SCLK_POST_EN 104 -#define AUD_CLKID_MST_B_SCLK_POST_EN 105 -#define AUD_CLKID_MST_C_SCLK_POST_EN 106 -#define AUD_CLKID_MST_D_SCLK_POST_EN 107 -#define AUD_CLKID_MST_E_SCLK_POST_EN 108 -#define AUD_CLKID_MST_F_SCLK_POST_EN 109 -#define AUD_CLKID_MST_A_LRCLK_DIV 110 -#define AUD_CLKID_MST_B_LRCLK_DIV 111 -#define AUD_CLKID_MST_C_LRCLK_DIV 112 -#define AUD_CLKID_MST_D_LRCLK_DIV 113 -#define AUD_CLKID_MST_E_LRCLK_DIV 114 -#define AUD_CLKID_MST_F_LRCLK_DIV 115 -#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137 -#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138 -#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139 -#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140 -#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141 -#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142 -#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143 -#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144 -#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145 -#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146 -#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147 -#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148 -#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149 -#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150 -#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153 -#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154 -#define AUD_CLKID_CLK81_EN 173 -#define AUD_CLKID_SYSCLK_A_DIV 174 -#define AUD_CLKID_SYSCLK_B_DIV 175 -#define AUD_CLKID_SYSCLK_A_EN 176 -#define AUD_CLKID_SYSCLK_B_EN 177 /* include the CLKIDs which are part of the DT bindings */ #include diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h index f561f5c5ef8f..08c82c22fa5f 100644 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -37,6 +37,26 @@ #define AUD_CLKID_SPDIFIN_CLK 56 #define AUD_CLKID_PDM_DCLK 57 #define AUD_CLKID_PDM_SYSCLK 58 +#define AUD_CLKID_MST_A_MCLK_SEL 59 +#define AUD_CLKID_MST_B_MCLK_SEL 60 +#define AUD_CLKID_MST_C_MCLK_SEL 61 +#define AUD_CLKID_MST_D_MCLK_SEL 62 +#define AUD_CLKID_MST_E_MCLK_SEL 63 +#define AUD_CLKID_MST_F_MCLK_SEL 64 +#define AUD_CLKID_MST_A_MCLK_DIV 65 +#define AUD_CLKID_MST_B_MCLK_DIV 66 +#define AUD_CLKID_MST_C_MCLK_DIV 67 +#define AUD_CLKID_MST_D_MCLK_DIV 68 +#define AUD_CLKID_MST_E_MCLK_DIV 69 +#define AUD_CLKID_MST_F_MCLK_DIV 70 +#define AUD_CLKID_SPDIFOUT_CLK_SEL 71 +#define AUD_CLKID_SPDIFOUT_CLK_DIV 72 +#define AUD_CLKID_SPDIFIN_CLK_SEL 73 +#define AUD_CLKID_SPDIFIN_CLK_DIV 74 +#define AUD_CLKID_PDM_DCLK_SEL 75 +#define AUD_CLKID_PDM_DCLK_DIV 76 +#define AUD_CLKID_PDM_SYSCLK_SEL 77 +#define AUD_CLKID_PDM_SYSCLK_DIV 78 #define AUD_CLKID_MST_A_SCLK 79 #define AUD_CLKID_MST_B_SCLK 80 #define AUD_CLKID_MST_C_SCLK 81 @@ -49,6 +69,30 @@ #define AUD_CLKID_MST_D_LRCLK 89 #define AUD_CLKID_MST_E_LRCLK 90 #define AUD_CLKID_MST_F_LRCLK 91 +#define AUD_CLKID_MST_A_SCLK_PRE_EN 92 +#define AUD_CLKID_MST_B_SCLK_PRE_EN 93 +#define AUD_CLKID_MST_C_SCLK_PRE_EN 94 +#define AUD_CLKID_MST_D_SCLK_PRE_EN 95 +#define AUD_CLKID_MST_E_SCLK_PRE_EN 96 +#define AUD_CLKID_MST_F_SCLK_PRE_EN 97 +#define AUD_CLKID_MST_A_SCLK_DIV 98 +#define AUD_CLKID_MST_B_SCLK_DIV 99 +#define AUD_CLKID_MST_C_SCLK_DIV 100 +#define AUD_CLKID_MST_D_SCLK_DIV 101 +#define AUD_CLKID_MST_E_SCLK_DIV 102 +#define AUD_CLKID_MST_F_SCLK_DIV 103 +#define AUD_CLKID_MST_A_SCLK_POST_EN 104 +#define AUD_CLKID_MST_B_SCLK_POST_EN 105 +#define AUD_CLKID_MST_C_SCLK_POST_EN 106 +#define AUD_CLKID_MST_D_SCLK_POST_EN 107 +#define AUD_CLKID_MST_E_SCLK_POST_EN 108 +#define AUD_CLKID_MST_F_SCLK_POST_EN 109 +#define AUD_CLKID_MST_A_LRCLK_DIV 110 +#define AUD_CLKID_MST_B_LRCLK_DIV 111 +#define AUD_CLKID_MST_C_LRCLK_DIV 112 +#define AUD_CLKID_MST_D_LRCLK_DIV 113 +#define AUD_CLKID_MST_E_LRCLK_DIV 114 +#define AUD_CLKID_MST_F_LRCLK_DIV 115 #define AUD_CLKID_TDMIN_A_SCLK_SEL 116 #define AUD_CLKID_TDMIN_B_SCLK_SEL 117 #define AUD_CLKID_TDMIN_C_SCLK_SEL 118 @@ -70,8 +114,24 @@ #define AUD_CLKID_TDMOUT_A_LRCLK 134 #define AUD_CLKID_TDMOUT_B_LRCLK 135 #define AUD_CLKID_TDMOUT_C_LRCLK 136 +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137 +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138 +#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139 +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140 +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141 +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142 +#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143 +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144 +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145 +#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146 +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147 +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148 +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149 +#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150 #define AUD_CLKID_SPDIFOUT_B 151 #define AUD_CLKID_SPDIFOUT_B_CLK 152 +#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153 +#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154 #define AUD_CLKID_TDM_MCLK_PAD0 155 #define AUD_CLKID_TDM_MCLK_PAD1 156 #define AUD_CLKID_TDM_LRCLK_PAD0 157 @@ -90,5 +150,10 @@ #define AUD_CLKID_FRDDR_D 170 #define AUD_CLKID_TODDR_D 171 #define AUD_CLKID_LOOPBACK_B 172 +#define AUD_CLKID_CLK81_EN 173 +#define AUD_CLKID_SYSCLK_A_DIV 174 +#define AUD_CLKID_SYSCLK_B_DIV 175 +#define AUD_CLKID_SYSCLK_A_EN 176 +#define AUD_CLKID_SYSCLK_B_EN 177 #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ -- cgit v1.2.3 From df873243b2398a082d34a006bebe0e0ed7538f5c Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 3 Aug 2023 16:27:34 +0530 Subject: dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock bindings for QDU1000 and QRU1000 SoCs. While at it, update the maintainers list. Signed-off-by: Imran Shaik Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++- include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml index 767a9d03aa32..d712b1a87e25 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 maintainers: - - Melody Olvera + - Taniya Das + - Imran Shaik description: | Qualcomm global clock control module which supports the clocks, resets and diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h index ddbc6b825e80..2fd36cbfddbb 100644 --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ /* - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H @@ -138,6 +138,8 @@ #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 #define GCC_PCIE_0_PIPE_CLK_SRC 129 #define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 +#define GCC_GPLL1_OUT_EVEN 131 +#define GCC_DDRSS_ECPRI_GSI_CLK 132 /* GCC resets */ #define GCC_ECPRI_CC_BCR 0 -- cgit v1.2.3 From 593576a369ec885275a1a368a6838844b78b4f35 Mon Sep 17 00:00:00 2001 From: Otto Pflüger Date: Wed, 2 Aug 2023 19:03:16 +0200 Subject: dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the missing #define for GPLL0_SLEEP_CLK_SRC, the parent clock of GPLL0_EARLY. Signed-off-by: Otto Pflüger Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230802170317.205112-2-otto.pflueger@abscue.de Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,gcc-msm8917.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h index a371b1adc896..4b421e7414b5 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8917.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h @@ -169,6 +169,7 @@ #define VFE0_CLK_SRC 162 #define VFE1_CLK_SRC 163 #define VSYNC_CLK_SRC 164 +#define GPLL0_SLEEP_CLK_SRC 165 /* GCC block resets */ #define GCC_CAMSS_MICRO_BCR 0 -- cgit v1.2.3 From a70cd8cdf7492006b547f46cc365eed79d331323 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 25 Jul 2023 12:56:23 +0800 Subject: dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support Add the clock dt-binding file for Audio Clock Mux. which is the IP for i.MX8QM, i.MX8QXP, i.MX8DXL. Add the clockid for clocks in header file. The Audio Clock Mux is binded with all the audio IP and audio clocks in the subsystem, so need to list the power domain of related clocks and IPs. Each clock and IP has a power domain, so there are so many power domains. Signed-off-by: Shengjiu Wang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1690260984-25744-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa --- .../devicetree/bindings/clock/fsl,imx8-acm.yaml | 282 +++++++++++++++++++++ include/dt-bindings/clock/imx8-clock.h | 28 ++ 2 files changed, 310 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml (limited to 'include/dt-bindings/clock') diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml b/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml new file mode 100644 index 000000000000..07b9d21719c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml @@ -0,0 +1,282 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8 Audio Clock Mux + +maintainers: + - Shengjiu Wang + +description: | + NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP + used to control Audio related clock on the SoC. + +properties: + compatible: + enum: + - fsl,imx8dxl-acm + - fsl,imx8qm-acm + - fsl,imx8qxp-acm + + reg: + maxItems: 1 + + power-domains: + minItems: 13 + maxItems: 21 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h + for the full list of i.MX8 ACM clock IDs. + + clocks: + minItems: 13 + maxItems: 27 + + clock-names: + minItems: 13 + maxItems: 27 + +required: + - compatible + - reg + - power-domains + - '#clock-cells' + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-acm + then: + properties: + power-domains: + items: + - description: power domain of IMX_SC_R_AUDIO_CLK_0 + - description: power domain of IMX_SC_R_AUDIO_CLK_1 + - description: power domain of IMX_SC_R_MCLK_OUT_0 + - description: power domain of IMX_SC_R_MCLK_OUT_1 + - description: power domain of IMX_SC_R_AUDIO_PLL_0 + - description: power domain of IMX_SC_R_AUDIO_PLL_1 + - description: power domain of IMX_SC_R_ASRC_0 + - description: power domain of IMX_SC_R_ASRC_1 + - description: power domain of IMX_SC_R_ESAI_0 + - description: power domain of IMX_SC_R_SAI_0 + - description: power domain of IMX_SC_R_SAI_1 + - description: power domain of IMX_SC_R_SAI_2 + - description: power domain of IMX_SC_R_SAI_3 + - description: power domain of IMX_SC_R_SAI_4 + - description: power domain of IMX_SC_R_SAI_5 + - description: power domain of IMX_SC_R_SPDIF_0 + - description: power domain of IMX_SC_R_MQS_0 + + clocks: + minItems: 18 + maxItems: 18 + + clock-names: + items: + - const: aud_rec_clk0_lpcg_clk + - const: aud_rec_clk1_lpcg_clk + - const: aud_pll_div_clk0_lpcg_clk + - const: aud_pll_div_clk1_lpcg_clk + - const: ext_aud_mclk0 + - const: ext_aud_mclk1 + - const: esai0_rx_clk + - const: esai0_rx_hf_clk + - const: esai0_tx_clk + - const: esai0_tx_hf_clk + - const: spdif0_rx + - const: sai0_rx_bclk + - const: sai0_tx_bclk + - const: sai1_rx_bclk + - const: sai1_tx_bclk + - const: sai2_rx_bclk + - const: sai3_rx_bclk + - const: sai4_rx_bclk + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-acm + then: + properties: + power-domains: + items: + - description: power domain of IMX_SC_R_AUDIO_CLK_0 + - description: power domain of IMX_SC_R_AUDIO_CLK_1 + - description: power domain of IMX_SC_R_MCLK_OUT_0 + - description: power domain of IMX_SC_R_MCLK_OUT_1 + - description: power domain of IMX_SC_R_AUDIO_PLL_0 + - description: power domain of IMX_SC_R_AUDIO_PLL_1 + - description: power domain of IMX_SC_R_ASRC_0 + - description: power domain of IMX_SC_R_ASRC_1 + - description: power domain of IMX_SC_R_ESAI_0 + - description: power domain of IMX_SC_R_ESAI_1 + - description: power domain of IMX_SC_R_SAI_0 + - description: power domain of IMX_SC_R_SAI_1 + - description: power domain of IMX_SC_R_SAI_2 + - description: power domain of IMX_SC_R_SAI_3 + - description: power domain of IMX_SC_R_SAI_4 + - description: power domain of IMX_SC_R_SAI_5 + - description: power domain of IMX_SC_R_SAI_6 + - description: power domain of IMX_SC_R_SAI_7 + - description: power domain of IMX_SC_R_SPDIF_0 + - description: power domain of IMX_SC_R_SPDIF_1 + - description: power domain of IMX_SC_R_MQS_0 + + clocks: + minItems: 27 + maxItems: 27 + + clock-names: + items: + - const: aud_rec_clk0_lpcg_clk + - const: aud_rec_clk1_lpcg_clk + - const: aud_pll_div_clk0_lpcg_clk + - const: aud_pll_div_clk1_lpcg_clk + - const: mlb_clk + - const: hdmi_rx_mclk + - const: ext_aud_mclk0 + - const: ext_aud_mclk1 + - const: esai0_rx_clk + - const: esai0_rx_hf_clk + - const: esai0_tx_clk + - const: esai0_tx_hf_clk + - const: esai1_rx_clk + - const: esai1_rx_hf_clk + - const: esai1_tx_clk + - const: esai1_tx_hf_clk + - const: spdif0_rx + - const: spdif1_rx + - const: sai0_rx_bclk + - const: sai0_tx_bclk + - const: sai1_rx_bclk + - const: sai1_tx_bclk + - const: sai2_rx_bclk + - const: sai3_rx_bclk + - const: sai4_rx_bclk + - const: sai5_tx_bclk + - const: sai6_rx_bclk + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8dxl-acm + then: + properties: + power-domains: + items: + - description: power domain of IMX_SC_R_AUDIO_CLK_0 + - description: power domain of IMX_SC_R_AUDIO_CLK_1 + - description: power domain of IMX_SC_R_MCLK_OUT_0 + - description: power domain of IMX_SC_R_MCLK_OUT_1 + - description: power domain of IMX_SC_R_AUDIO_PLL_0 + - description: power domain of IMX_SC_R_AUDIO_PLL_1 + - description: power domain of IMX_SC_R_ASRC_0 + - description: power domain of IMX_SC_R_SAI_0 + - description: power domain of IMX_SC_R_SAI_1 + - description: power domain of IMX_SC_R_SAI_2 + - description: power domain of IMX_SC_R_SAI_3 + - description: power domain of IMX_SC_R_SPDIF_0 + - description: power domain of IMX_SC_R_MQS_0 + + clocks: + minItems: 13 + maxItems: 13 + + clock-names: + items: + - const: aud_rec_clk0_lpcg_clk + - const: aud_rec_clk1_lpcg_clk + - const: aud_pll_div_clk0_lpcg_clk + - const: aud_pll_div_clk1_lpcg_clk + - const: ext_aud_mclk0 + - const: ext_aud_mclk1 + - const: spdif0_rx + - const: sai0_rx_bclk + - const: sai0_tx_bclk + - const: sai1_rx_bclk + - const: sai1_tx_bclk + - const: sai2_rx_bclk + - const: sai3_rx_bclk + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include + #include + + clock-controller@59e00000 { + compatible = "fsl,imx8qxp-acm"; + reg = <0x59e00000 0x1d0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_esai0_rx_clk>, + <&clk_esai0_rx_hf_clk>, + <&clk_esai0_tx_clk>, + <&clk_esai0_tx_hf_clk>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>, + <&clk_sai4_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk"; + }; diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 2e60ce4d2622..2242ff54fc5e 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -164,4 +164,32 @@ #define IMX_ADMA_LPCG_CLK_END 45 +#define IMX_ADMA_ACM_AUD_CLK0_SEL 0 +#define IMX_ADMA_ACM_AUD_CLK1_SEL 1 +#define IMX_ADMA_ACM_MCLKOUT0_SEL 2 +#define IMX_ADMA_ACM_MCLKOUT1_SEL 3 +#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 4 +#define IMX_ADMA_ACM_ESAI1_MCLK_SEL 5 +#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 6 +#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 7 +#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 8 +#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 9 +#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 10 +#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 11 +#define IMX_ADMA_ACM_SAI0_MCLK_SEL 12 +#define IMX_ADMA_ACM_SAI1_MCLK_SEL 13 +#define IMX_ADMA_ACM_SAI2_MCLK_SEL 14 +#define IMX_ADMA_ACM_SAI3_MCLK_SEL 15 +#define IMX_ADMA_ACM_SAI4_MCLK_SEL 16 +#define IMX_ADMA_ACM_SAI5_MCLK_SEL 17 +#define IMX_ADMA_ACM_SAI6_MCLK_SEL 18 +#define IMX_ADMA_ACM_SAI7_MCLK_SEL 19 +#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 20 +#define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL 21 +#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 22 +#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 23 +#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 24 + +#define IMX_ADMA_ACM_CLK_END 25 + #endif /* __DT_BINDINGS_CLOCK_IMX_H */ -- cgit v1.2.3 From 35ec2abb54726e1a72c570f6465811e049d81cbc Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 31 Jul 2023 16:21:50 +0200 Subject: dt-bindings: clocks: imx8mp: make sai4 a dummy clock The hardware don't have a SAI4 instance so remove the define. Use a comment to keep it as reference and to avoid confusion. Fixes: 108869144739 ("dt-bindings: imx: Add clock binding doc for i.MX8MP") Acked-by: Stephen Boyd Acked-by: Rob Herring Signed-off-by: Marco Felsch Link: https://lore.kernel.org/r/20230731142150.3186650-2-m.felsch@pengutronix.de Signed-off-by: Abel Vesa --- include/dt-bindings/clock/imx8mp-clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 3f28ce685f41..11cb0a4fe999 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -130,7 +130,7 @@ #define IMX8MP_CLK_SAI1 123 #define IMX8MP_CLK_SAI2 124 #define IMX8MP_CLK_SAI3 125 -#define IMX8MP_CLK_SAI4 126 +/* #define IMX8MP_CLK_SAI4 126 */ #define IMX8MP_CLK_SAI5 127 #define IMX8MP_CLK_SAI6 128 #define IMX8MP_CLK_ENET_QOS 129 -- cgit v1.2.3 From b3f9581affb03ed28ff1905b649e66904f29b9e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Aug 2023 10:27:38 +0200 Subject: dt-bindings: clock: samsung: remove define with number of clocks Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Remove it entirely from the bindings, once Linux drivers stopped using them. Reviewed-by: Conor Dooley Reviewed-by: Sam Protsenko Reviewed-by: Alim Akhtar Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20230808082738.122804-12-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/exynos3250.h | 18 ---------- include/dt-bindings/clock/exynos4.h | 5 --- include/dt-bindings/clock/exynos5250.h | 3 -- include/dt-bindings/clock/exynos5260-clk.h | 25 -------------- include/dt-bindings/clock/exynos5410.h | 2 -- include/dt-bindings/clock/exynos5420.h | 3 -- include/dt-bindings/clock/exynos5433.h | 42 ------------------------ include/dt-bindings/clock/exynos7885.h | 4 --- include/dt-bindings/clock/exynos850.h | 10 ------ include/dt-bindings/clock/samsung,exynosautov9.h | 18 ---------- 10 files changed, 130 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index fe8214017b46..cc7268151843 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -256,12 +256,6 @@ #define CLK_SCLK_UART2 248 #define CLK_SCLK_MMC2 249 -/* - * Total number of clocks of main CMU. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define CLK_NR_CLKS 250 - /* * CMU DMC */ @@ -283,12 +277,6 @@ #define CLK_DIV_DMCP 19 #define CLK_DIV_DMCD 20 -/* - * Total number of clocks of main CMU. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define NR_CLKS_DMC 21 - /* * CMU ISP */ @@ -344,10 +332,4 @@ #define CLK_ASYNCAXIM 46 #define CLK_SCLK_MPWM_ISP 47 -/* - * Total number of clocks of CMU_ISP. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define NR_CLKS_ISP 48 - #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index acbfbab875ec..4ebff79ed9e2 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -239,9 +239,6 @@ #define CLK_DIV_GDR 460 #define CLK_DIV_CORE2 461 -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 462 - /* Exynos4x12 ISP clocks */ #define CLK_ISP_FIMC_ISP 1 #define CLK_ISP_FIMC_DRC 2 @@ -275,6 +272,4 @@ #define CLK_ISP_DIV_MCUISP0 29 #define CLK_ISP_DIV_MCUISP1 30 -#define CLK_NR_ISP_CLKS 31 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index 4680da7357d3..2337c028bbe1 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -177,7 +177,4 @@ #define CLK_MOUT_MPLL 1029 #define CLK_MOUT_VPLLSRC 1030 -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 1031 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ diff --git a/include/dt-bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-clk.h index 98a58cbd81b2..dfde40ea40f0 100644 --- a/include/dt-bindings/clock/exynos5260-clk.h +++ b/include/dt-bindings/clock/exynos5260-clk.h @@ -137,8 +137,6 @@ #define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 -#define TOP_NR_CLK 125 - /* List Of Clocks For CMU_EGL */ @@ -153,8 +151,6 @@ #define EGL_DOUT_ACLK_EGL 9 #define EGL_DOUT_EGL2 10 #define EGL_DOUT_EGL1 11 -#define EGL_NR_CLK 12 - /* List Of Clocks For CMU_KFC */ @@ -168,8 +164,6 @@ #define KFC_DOUT_KFC_ATCLK 8 #define KFC_DOUT_KFC2 9 #define KFC_DOUT_KFC1 10 -#define KFC_NR_CLK 11 - /* List Of Clocks For CMU_MIF */ @@ -200,8 +194,6 @@ #define MIF_CLK_INTMEM 25 #define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 -#define MIF_NR_CLK 28 - /* List Of Clocks For CMU_G3D */ @@ -211,8 +203,6 @@ #define G3D_DOUT_ACLK_G3D 4 #define G3D_CLK_G3D_HPM 5 #define G3D_CLK_G3D 6 -#define G3D_NR_CLK 7 - /* List Of Clocks For CMU_AUD */ @@ -231,8 +221,6 @@ #define AUD_SCLK_AUD_UART 13 #define AUD_SCLK_PCM 14 #define AUD_SCLK_I2S 15 -#define AUD_NR_CLK 16 - /* List Of Clocks For CMU_MFC */ @@ -241,8 +229,6 @@ #define MFC_CLK_MFC 3 #define MFC_CLK_SMMU2_MFCM1 4 #define MFC_CLK_SMMU2_MFCM0 5 -#define MFC_NR_CLK 6 - /* List Of Clocks For CMU_GSCL */ @@ -272,8 +258,6 @@ #define GSCL_CLK_SMMU3_MSCL1 24 #define GSCL_SCLK_CSIS1_WRAP 25 #define GSCL_SCLK_CSIS0_WRAP 26 -#define GSCL_NR_CLK 27 - /* List Of Clocks For CMU_FSYS */ @@ -295,8 +279,6 @@ #define FSYS_CLK_SMMU_RTIC 16 #define FSYS_PHYCLK_USBDRD30 17 #define FSYS_PHYCLK_USBHOST20 18 -#define FSYS_NR_CLK 19 - /* List Of Clocks For CMU_PERI */ @@ -366,8 +348,6 @@ #define PERI_SCLK_SPDIF 64 #define PERI_SCLK_I2S 65 #define PERI_SCLK_PCM1 66 -#define PERI_NR_CLK 67 - /* List Of Clocks For CMU_DISP */ @@ -406,8 +386,6 @@ #define DISP_CLK_DP 33 #define DISP_SCLK_PIXEL 34 #define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 -#define DISP_NR_CLK 36 - /* List Of Clocks For CMU_G2D */ @@ -423,8 +401,6 @@ #define G2D_CLK_SMMU_SSS 10 #define G2D_CLK_SMMU_MDMA 11 #define G2D_CLK_SMMU3_G2D 12 -#define G2D_NR_CLK 13 - /* List Of Clocks For CMU_ISP */ @@ -461,6 +437,5 @@ #define ISP_SCLK_SPI0_EXT 31 #define ISP_SCLK_SPI1_EXT 32 #define ISP_SCLK_UART_EXT 33 -#define ISP_NR_CLK 34 #endif diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 86c2ad56c5ef..7a1a93f8df6c 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -61,6 +61,4 @@ #define CLK_USBD301 367 #define CLK_SSS 471 -#define CLK_NR_CLKS 512 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 9fffc6ceaadd..73e82527a9e9 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -271,7 +271,4 @@ #define CLK_DOUT_PCLK_DREX0 798 #define CLK_DOUT_PCLK_DREX1 799 -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 800 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 25ffa53573a5..d12c1a963fa1 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -188,8 +188,6 @@ #define CLK_SCLK_ISP_SPI0_CAM1 252 #define CLK_SCLK_HDMI_SPDIF_DISP 253 -#define TOP_NR_CLK 254 - /* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL 1 @@ -200,8 +198,6 @@ #define CLK_SCLK_MPHY_PLL 11 #define CLK_SCLK_UFS_MPHY 11 -#define CPIF_NR_CLK 12 - /* CMU_MIF */ #define CLK_FOUT_MEM0_PLL 1 #define CLK_FOUT_MEM1_PLL 2 @@ -396,8 +392,6 @@ #define CLK_SCLK_BUS_PLL_APOLLO 199 #define CLK_SCLK_BUS_PLL_ATLAS 200 -#define MIF_NR_CLK 201 - /* CMU_PERIC */ #define CLK_PCLK_SPI2 1 #define CLK_PCLK_SPI1 2 @@ -468,8 +462,6 @@ #define CLK_DIV_SCLK_SCI 70 #define CLK_DIV_SCLK_SC_IN 71 -#define PERIC_NR_CLK 72 - /* CMU_PERIS */ #define CLK_PCLK_HPM_APBIF 1 #define CLK_PCLK_TMU1_APBIF 2 @@ -513,8 +505,6 @@ #define CLK_SCLK_ANTIRBK_CNT 40 #define CLK_SCLK_OTP_CON 41 -#define PERIS_NR_CLK 42 - /* CMU_FSYS */ #define CLK_MOUT_ACLK_FSYS_200_USER 1 #define CLK_MOUT_SCLK_MMC2_USER 2 @@ -621,8 +611,6 @@ #define CLK_SCLK_USBDRD30 114 #define CLK_PCIE 115 -#define FSYS_NR_CLK 116 - /* CMU_G2D */ #define CLK_MUX_ACLK_G2D_266_USER 1 #define CLK_MUX_ACLK_G2D_400_USER 2 @@ -653,8 +641,6 @@ #define CLK_PCLK_G2D 25 #define CLK_PCLK_SMMU_G2D 26 -#define G2D_NR_CLK 27 - /* CMU_DISP */ #define CLK_FOUT_DISP_PLL 1 @@ -771,8 +757,6 @@ #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 -#define DISP_NR_CLK 116 - /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 #define CLK_MOUT_SCLK_AUD_PCM 2 @@ -824,8 +808,6 @@ #define CLK_SCLK_I2S_BCLK 46 #define CLK_SCLK_AUD_I2S 47 -#define AUD_NR_CLK 48 - /* CMU_BUS{0|1|2} */ #define CLK_DIV_PCLK_BUS_133 1 @@ -840,8 +822,6 @@ #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ -#define BUSx_NR_CLK 11 - /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 @@ -865,8 +845,6 @@ #define CLK_PCLK_SYSREG_G3D 18 #define CLK_SCLK_HPM_G3D 19 -#define G3D_NR_CLK 20 - /* CMU_GSCL */ #define CLK_MOUT_ACLK_GSCL_111_USER 1 #define CLK_MOUT_ACLK_GSCL_333_USER 2 @@ -898,8 +876,6 @@ #define CLK_PCLK_SMMU_GSCL1 27 #define CLK_PCLK_SMMU_GSCL2 28 -#define GSCL_NR_CLK 29 - /* CMU_APOLLO */ #define CLK_FOUT_APOLLO_PLL 1 @@ -935,8 +911,6 @@ #define CLK_SCLK_HPM_APOLLO 29 #define CLK_SCLK_APOLLO 30 -#define APOLLO_NR_CLK 31 - /* CMU_ATLAS */ #define CLK_FOUT_ATLAS_PLL 1 @@ -981,8 +955,6 @@ #define CLK_ATCLK 38 #define CLK_SCLK_ATLAS 39 -#define ATLAS_NR_CLK 40 - /* CMU_MSCL */ #define CLK_MOUT_SCLK_JPEG_USER 1 #define CLK_MOUT_ACLK_MSCL_400_USER 2 @@ -1016,8 +988,6 @@ #define CLK_PCLK_SMMU_JPEG 28 #define CLK_SCLK_JPEG 29 -#define MSCL_NR_CLK 30 - /* CMU_MFC */ #define CLK_MOUT_ACLK_MFC_400_USER 1 @@ -1040,8 +1010,6 @@ #define CLK_PCLK_SMMU_MFC_1 17 #define CLK_PCLK_SMMU_MFC_0 18 -#define MFC_NR_CLK 19 - /* CMU_HEVC */ #define CLK_MOUT_ACLK_HEVC_400_USER 1 @@ -1064,8 +1032,6 @@ #define CLK_PCLK_SMMU_HEVC_1 17 #define CLK_PCLK_SMMU_HEVC_0 18 -#define HEVC_NR_CLK 19 - /* CMU_ISP */ #define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 #define CLK_MOUT_ACLK_ISP_400_USER 2 @@ -1147,8 +1113,6 @@ #define CLK_SCLK_PIXELASYNCS_ISPC 76 #define CLK_SCLK_PIXELASYNCM_ISPC 77 -#define ISP_NR_CLK 78 - /* CMU_CAM0 */ #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 @@ -1285,8 +1249,6 @@ #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 -#define CAM0_NR_CLK 134 - /* CMU_CAM1 */ #define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1 @@ -1404,12 +1366,8 @@ #define CLK_ATCLK_ISP 111 #define CLK_SCLK_ISP_CA5 112 -#define CAM1_NR_CLK 113 - /* CMU_IMEM */ #define CLK_ACLK_SLIMSSS 2 #define CLK_PCLK_SLIMSSS 35 -#define IMEM_NR_CLK 36 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index 8256e7430b63..255e3aa94323 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -69,7 +69,6 @@ #define CLK_GOUT_FSYS_MMC_EMBD 58 #define CLK_GOUT_FSYS_MMC_SDIO 59 #define CLK_GOUT_FSYS_USB30DRD 60 -#define TOP_NR_CLK 61 /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 @@ -86,7 +85,6 @@ #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12 #define CLK_GOUT_TREX_P_CORE_PCLK 13 #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14 -#define CORE_NR_CLK 15 /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 @@ -132,7 +130,6 @@ #define CLK_GOUT_SYSREG_PERI_PCLK 41 #define CLK_GOUT_WDT0_PCLK 42 #define CLK_GOUT_WDT1_PCLK 43 -#define PERI_NR_CLK 44 /* CMU_FSYS */ #define CLK_MOUT_FSYS_BUS_USER 1 @@ -146,6 +143,5 @@ #define CLK_GOUT_MMC_EMBD_SDCLKIN 8 #define CLK_GOUT_MMC_SDIO_ACLK 9 #define CLK_GOUT_MMC_SDIO_SDCLKIN 10 -#define FSYS_NR_CLK 11 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index afacba338c91..3090e09c9a55 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -88,7 +88,6 @@ #define CLK_MOUT_G3D_SWITCH 76 #define CLK_GOUT_G3D_SWITCH 77 #define CLK_DOUT_G3D_SWITCH 78 -#define TOP_NR_CLK 79 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -115,7 +114,6 @@ #define CLK_GOUT_GPIO_ALIVE_PCLK 22 #define CLK_GOUT_PMU_ALIVE_PCLK 23 #define CLK_GOUT_SYSREG_APM_PCLK 24 -#define APM_NR_CLK 25 /* CMU_AUD */ #define CLK_DOUT_AUD_AUDIF 1 @@ -179,7 +177,6 @@ #define IOCLK_AUDIOCDCLK6 59 #define TICK_USB 60 #define CLK_GOUT_AUD_CMU_AUD_PCLK 61 -#define AUD_NR_CLK 62 /* CMU_CMGP */ #define CLK_RCO_CMGP 1 @@ -197,7 +194,6 @@ #define CLK_GOUT_CMGP_USI1_IPCLK 13 #define CLK_GOUT_CMGP_USI1_PCLK 14 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 -#define CMGP_NR_CLK 16 /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 @@ -212,7 +208,6 @@ #define CLK_GOUT_G3D_BUSD_CLK 10 #define CLK_GOUT_G3D_BUSP_CLK 11 #define CLK_GOUT_G3D_SYSREG_PCLK 12 -#define G3D_NR_CLK 13 /* CMU_HSI */ #define CLK_MOUT_HSI_BUS_USER 1 @@ -231,7 +226,6 @@ #define CLK_GOUT_HSI_PPMU_ACLK 14 #define CLK_GOUT_HSI_PPMU_PCLK 15 #define CLK_GOUT_HSI_CMU_HSI_PCLK 16 -#define HSI_NR_CLK 17 /* CMU_IS */ #define CLK_MOUT_IS_BUS_USER 1 @@ -257,7 +251,6 @@ #define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 #define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 #define CLK_GOUT_IS_SYSREG_PCLK 23 -#define IS_NR_CLK 24 /* CMU_MFCMSCL */ #define CLK_MOUT_MFCMSCL_MFC_USER 1 @@ -275,7 +268,6 @@ #define CLK_GOUT_MFCMSCL_PPMU_PCLK 13 #define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14 #define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15 -#define MFCMSCL_NR_CLK 16 /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 @@ -312,7 +304,6 @@ #define CLK_GOUT_UART_PCLK 32 #define CLK_GOUT_WDT0_PCLK 33 #define CLK_GOUT_WDT1_PCLK 34 -#define PERI_NR_CLK 35 /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 @@ -329,7 +320,6 @@ #define CLK_GOUT_SSS_PCLK 12 #define CLK_GOUT_GPIO_CORE_PCLK 13 #define CLK_GOUT_SYSREG_CORE_PCLK 14 -#define CORE_NR_CLK 15 /* CMU_DPU */ #define CLK_MOUT_DPU_USER 1 diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h index 42133af6d6b9..3065375c2d8b 100644 --- a/include/dt-bindings/clock/samsung,exynosautov9.h +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -166,16 +166,12 @@ #define GOUT_CLKCMU_PERIC1_IP 248 #define GOUT_CLKCMU_PERIS_BUS 249 -#define TOP_NR_CLK 250 - /* CMU_BUSMC */ #define CLK_MOUT_BUSMC_BUS_USER 1 #define CLK_DOUT_BUSMC_BUSP 2 #define CLK_GOUT_BUSMC_PDMA0_PCLK 3 #define CLK_GOUT_BUSMC_SPDMA_PCLK 4 -#define BUSMC_NR_CLK 5 - /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 #define CLK_DOUT_CORE_BUSP 2 @@ -183,8 +179,6 @@ #define CLK_GOUT_CORE_CCI_PCLK 4 #define CLK_GOUT_CORE_CMU_CORE_PCLK 5 -#define CORE_NR_CLK 6 - /* CMU_FSYS0 */ #define CLK_MOUT_FSYS0_BUS_USER 1 #define CLK_MOUT_FSYS0_PCIE_USER 2 @@ -226,8 +220,6 @@ #define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35 #define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36 -#define FSYS0_NR_CLK 37 - /* CMU_FSYS1 */ #define FOUT_MMC_PLL 1 @@ -251,8 +243,6 @@ #define CLK_GOUT_FSYS1_USB30_0_ACLK 17 #define CLK_GOUT_FSYS1_USB30_1_ACLK 18 -#define FSYS1_NR_CLK 19 - /* CMU_FSYS2 */ #define CLK_MOUT_FSYS2_BUS_USER 1 #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2 @@ -262,8 +252,6 @@ #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6 #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7 -#define FSYS2_NR_CLK 8 - /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_BUS_USER 1 #define CLK_MOUT_PERIC0_IP_USER 2 @@ -308,8 +296,6 @@ #define CLK_GOUT_PERIC0_PCLK_10 42 #define CLK_GOUT_PERIC0_PCLK_11 43 -#define PERIC0_NR_CLK 44 - /* CMU_PERIC1 */ #define CLK_MOUT_PERIC1_BUS_USER 1 #define CLK_MOUT_PERIC1_IP_USER 2 @@ -354,14 +340,10 @@ #define CLK_GOUT_PERIC1_PCLK_10 42 #define CLK_GOUT_PERIC1_PCLK_11 43 -#define PERIC1_NR_CLK 44 - /* CMU_PERIS */ #define CLK_MOUT_PERIS_BUS_USER 1 #define CLK_GOUT_SYSREG_PERIS_PCLK 2 #define CLK_GOUT_WDT_CLUSTER0 3 #define CLK_GOUT_WDT_CLUSTER1 4 -#define PERIS_NR_CLK 5 - #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */ -- cgit v1.2.3 From 268edfe96ab8de82f1ba64a2098610e256bd6db7 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 14 Aug 2023 12:40:23 +0200 Subject: dt-bindings: clock: qcom: ipq4019: add missing networking resets Add bindings for the missing networking resets found in IPQ4019 GCC. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,gcc-ipq4019.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h index 7e8a7be6dcda..fa0587857547 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h @@ -165,5 +165,11 @@ #define GCC_QDSS_BCR 69 #define GCC_MPM_BCR 70 #define GCC_SPDM_BCR 71 +#define ESS_MAC1_ARES 72 +#define ESS_MAC2_ARES 73 +#define ESS_MAC3_ARES 74 +#define ESS_MAC4_ARES 75 +#define ESS_MAC5_ARES 76 +#define ESS_PSGMII_ARES 77 #endif -- cgit v1.2.3 From 46c13513a4af9e5ca8b286ab8f3afecb1404282a Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Sat, 12 Aug 2023 12:02:56 +0200 Subject: clk: mmp2: Move number of clocks to driver source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-1-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-audio.c | 6 ++++-- drivers/clk/mmp/clk-of-mmp2.c | 4 +++- include/dt-bindings/clock/marvell,mmp2-audio.h | 1 - include/dt-bindings/clock/marvell,mmp2.h | 1 - 4 files changed, 7 insertions(+), 5 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/mmp/clk-audio.c b/drivers/clk/mmp/clk-audio.c index 6fb1aa9487b5..ae521aaf8cdc 100644 --- a/drivers/clk/mmp/clk-audio.c +++ b/drivers/clk/mmp/clk-audio.c @@ -55,6 +55,8 @@ #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK (0x7ff << 0) #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(x) ((x) << 0) +#define CLK_AUDIO_NR_CLKS 3 + struct mmp2_audio_clk { void __iomem *mmio_base; @@ -336,7 +338,7 @@ static int register_clocks(struct mmp2_audio_clk *priv, struct device *dev) priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw; priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw; priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw; - priv->clk_data.num = MMP2_CLK_AUDIO_NR_CLKS; + priv->clk_data.num = CLK_AUDIO_NR_CLKS; return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, &priv->clk_data); @@ -349,7 +351,7 @@ static int mmp2_audio_clk_probe(struct platform_device *pdev) priv = devm_kzalloc(&pdev->dev, struct_size(priv, clk_data.hws, - MMP2_CLK_AUDIO_NR_CLKS), + CLK_AUDIO_NR_CLKS), GFP_KERNEL); if (!priv) return -ENOMEM; diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index bcf60f43aa13..eaad36ee323d 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -78,6 +78,8 @@ #define MPMU_PLL_DIFF_CTRL 0x68 #define MPMU_PLL2_CTRL1 0x414 +#define NR_CLKS 200 + enum mmp2_clk_model { CLK_MODEL_MMP2, CLK_MODEL_MMP3, @@ -543,7 +545,7 @@ static void __init mmp2_clk_init(struct device_node *np) mmp2_pm_domain_init(np, pxa_unit); - mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, NR_CLKS); mmp2_main_clk_init(pxa_unit); diff --git a/include/dt-bindings/clock/marvell,mmp2-audio.h b/include/dt-bindings/clock/marvell,mmp2-audio.h index 20664776f497..9653e04dedc3 100644 --- a/include/dt-bindings/clock/marvell,mmp2-audio.h +++ b/include/dt-bindings/clock/marvell,mmp2-audio.h @@ -6,5 +6,4 @@ #define MMP2_CLK_AUDIO_SSPA0 1 #define MMP2_CLK_AUDIO_SSPA1 2 -#define MMP2_CLK_AUDIO_NR_CLKS 3 #endif diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h index f0819d66b230..88c2d716476f 100644 --- a/include/dt-bindings/clock/marvell,mmp2.h +++ b/include/dt-bindings/clock/marvell,mmp2.h @@ -91,5 +91,4 @@ #define MMP3_CLK_SDH4 126 #define MMP2_CLK_AUDIO 127 -#define MMP2_NR_CLKS 200 #endif -- cgit v1.2.3 From 51fa6aa5c2c2b85b6ddaab267cf03ef30417ef67 Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Sat, 12 Aug 2023 12:02:57 +0200 Subject: clk: pxa168: Move number of clocks to driver source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-2-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-of-pxa168.c | 4 +++- include/dt-bindings/clock/marvell,pxa168.h | 1 - 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c index 130d1a723879..fb0df64cf053 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -62,6 +62,8 @@ #define APMU_EPD 0x104 #define MPMU_UART_PLL 0x14 +#define NR_CLKS 200 + struct pxa168_clk_unit { struct mmp_clk_unit unit; void __iomem *mpmu_base; @@ -321,7 +323,7 @@ static void __init pxa168_clk_init(struct device_node *np) return; } - mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, NR_CLKS); pxa168_pll_init(pxa_unit); diff --git a/include/dt-bindings/clock/marvell,pxa168.h b/include/dt-bindings/clock/marvell,pxa168.h index c92d969ae941..d1bb59187e1d 100644 --- a/include/dt-bindings/clock/marvell,pxa168.h +++ b/include/dt-bindings/clock/marvell,pxa168.h @@ -63,5 +63,4 @@ #define PXA168_CLK_SDH01_AXI 111 #define PXA168_CLK_SDH23_AXI 112 -#define PXA168_NR_CLKS 200 #endif -- cgit v1.2.3 From 87f06247e031dc7bbc864efecb6feb77d452813f Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Sat, 12 Aug 2023 12:02:58 +0200 Subject: clk: pxa1928: Move number of clocks to driver source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-3-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-of-pxa1928.c | 7 +++++-- include/dt-bindings/clock/marvell,pxa1928.h | 3 --- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c index 2508a0d795f8..9def4b5f10e9 100644 --- a/drivers/clk/mmp/clk-of-pxa1928.c +++ b/drivers/clk/mmp/clk-of-pxa1928.c @@ -22,6 +22,9 @@ #define MPMU_UART_PLL 0x14 +#define APBC_NR_CLKS 48 +#define APMU_NR_CLKS 96 + struct pxa1928_clk_unit { struct mmp_clk_unit unit; void __iomem *mpmu_base; @@ -235,7 +238,7 @@ static void __init pxa1928_apmu_clk_init(struct device_node *np) return; } - mmp_clk_init(np, &pxa_unit->unit, PXA1928_APMU_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, APMU_NR_CLKS); pxa1928_axi_periph_clk_init(pxa_unit); } @@ -256,7 +259,7 @@ static void __init pxa1928_apbc_clk_init(struct device_node *np) return; } - mmp_clk_init(np, &pxa_unit->unit, PXA1928_APBC_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS); pxa1928_apb_periph_clk_init(pxa_unit); pxa1928_clk_reset_init(np, pxa_unit); diff --git a/include/dt-bindings/clock/marvell,pxa1928.h b/include/dt-bindings/clock/marvell,pxa1928.h index 5dca4820297f..0c708d3d3314 100644 --- a/include/dt-bindings/clock/marvell,pxa1928.h +++ b/include/dt-bindings/clock/marvell,pxa1928.h @@ -36,7 +36,6 @@ #define PXA1928_CLK_THSENS_CPU 0x26 #define PXA1928_CLK_THSENS_VPU 0x27 #define PXA1928_CLK_THSENS_GC 0x28 -#define PXA1928_APBC_NR_CLKS 0x30 /* axi peripherals */ @@ -53,6 +52,4 @@ #define PXA1928_CLK_GC3D 0x5d #define PXA1928_CLK_GC2D 0x5f -#define PXA1928_APMU_NR_CLKS 0x60 - #endif -- cgit v1.2.3 From 3b99cd274e43b89c89a4072c602b1df6000eb1f4 Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Sat, 12 Aug 2023 12:02:59 +0200 Subject: clk: pxa910: Move number of clocks to driver source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-4-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-of-pxa910.c | 4 +++- include/dt-bindings/clock/marvell,pxa910.h | 1 - 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c index 4d15bac987eb..7a38c424782e 100644 --- a/drivers/clk/mmp/clk-of-pxa910.c +++ b/drivers/clk/mmp/clk-of-pxa910.c @@ -44,6 +44,8 @@ #define APMU_DFC 0x60 #define MPMU_UART_PLL 0x14 +#define NR_CLKS 200 + struct pxa910_clk_unit { struct mmp_clk_unit unit; void __iomem *mpmu_base; @@ -296,7 +298,7 @@ static void __init pxa910_clk_init(struct device_node *np) goto unmap_apbc_region; } - mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS); + mmp_clk_init(np, &pxa_unit->unit, NR_CLKS); pxa910_pll_init(pxa_unit); diff --git a/include/dt-bindings/clock/marvell,pxa910.h b/include/dt-bindings/clock/marvell,pxa910.h index c9018ab354d0..6caa231de0c1 100644 --- a/include/dt-bindings/clock/marvell,pxa910.h +++ b/include/dt-bindings/clock/marvell,pxa910.h @@ -55,5 +55,4 @@ #define PXA910_CLK_CCIC0_PHY 108 #define PXA910_CLK_CCIC0_SPHY 109 -#define PXA910_NR_CLKS 200 #endif -- cgit v1.2.3