From d48f12d9ae73c76f792eaaf057d4e64900730c0e Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 14 Sep 2021 14:52:00 +0800 Subject: dt-bindings: clock: Add imx8ulp clock support Add the clock dt-binding file for i.MX8ULP. For pcc node, it will also be used as a reset controller, so add the '#reset-cells' property description and add the pcc reset IDs. Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210914065208.3582128-2-ping.bai@nxp.com Signed-off-by: Abel Vesa --- include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h (limited to 'include/dt-bindings/reset') diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h new file mode 100644 index 000000000000..e99a4735c3c4 --- /dev/null +++ b/include/dt-bindings/reset/imx8ulp-pcc-reset.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2021 NXP + */ + +#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H +#define DT_BINDING_PCC_RESET_IMX8ULP_H + +/* PCC3 */ +#define PCC3_WDOG3_SWRST 0 +#define PCC3_WDOG4_SWRST 1 +#define PCC3_LPIT1_SWRST 2 +#define PCC3_TPM4_SWRST 3 +#define PCC3_TPM5_SWRST 4 +#define PCC3_FLEXIO1_SWRST 5 +#define PCC3_I3C2_SWRST 6 +#define PCC3_LPI2C4_SWRST 7 +#define PCC3_LPI2C5_SWRST 8 +#define PCC3_LPUART4_SWRST 9 +#define PCC3_LPUART5_SWRST 10 +#define PCC3_LPSPI4_SWRST 11 +#define PCC3_LPSPI5_SWRST 12 + +/* PCC4 */ +#define PCC4_FLEXSPI2_SWRST 0 +#define PCC4_TPM6_SWRST 1 +#define PCC4_TPM7_SWRST 2 +#define PCC4_LPI2C6_SWRST 3 +#define PCC4_LPI2C7_SWRST 4 +#define PCC4_LPUART6_SWRST 5 +#define PCC4_LPUART7_SWRST 6 +#define PCC4_SAI4_SWRST 7 +#define PCC4_SAI5_SWRST 8 +#define PCC4_USDHC0_SWRST 9 +#define PCC4_USDHC1_SWRST 10 +#define PCC4_USDHC2_SWRST 11 +#define PCC4_USB0_SWRST 12 +#define PCC4_USB0_PHY_SWRST 13 +#define PCC4_USB1_SWRST 14 +#define PCC4_USB1_PHY_SWRST 15 +#define PCC4_ENET_SWRST 16 + +/* PCC5 */ +#define PCC5_TPM8_SWRST 0 +#define PCC5_SAI6_SWRST 1 +#define PCC5_SAI7_SWRST 2 +#define PCC5_SPDIF_SWRST 3 +#define PCC5_ISI_SWRST 4 +#define PCC5_CSI_REGS_SWRST 5 +#define PCC5_CSI_SWRST 6 +#define PCC5_DSI_SWRST 7 +#define PCC5_WDOG5_SWRST 8 +#define PCC5_EPDC_SWRST 9 +#define PCC5_PXP_SWRST 10 +#define PCC5_GPU2D_SWRST 11 +#define PCC5_GPU3D_SWRST 12 +#define PCC5_DC_NANO_SWRST 13 + +#endif /*DT_BINDING_RESET_IMX8ULP_H */ -- cgit v1.2.3 From f2b883bbdd08b32f4c52cc95bccb4defae6ebf74 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 21 Sep 2021 20:48:02 +0200 Subject: dt-bindings: clock: u8500: Rewrite in YAML and extend This rewrites the ux500/u8500 clock bindings in YAML schema and extends them with the PRCC reset controller. The bindings are a bit idiomatic but it just reflects their age, the ux500 platform was used as guinea pig for early device tree conversion of platforms in 2015. The new subnode for the reset controller follows the pattern of the old bindings and adds a node with reset-cells for this. Cc: devicetree@vger.kernel.org Cc: Philipp Zabel Reviewed-by: Rob Herring Acked-by: Ulf Hansson Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20210921184803.1757916-1-linus.walleij@linaro.org Signed-off-by: Stephen Boyd --- .../bindings/clock/stericsson,u8500-clks.yaml | 121 +++++++++++++++++++++ Documentation/devicetree/bindings/clock/ux500.txt | 64 ----------- .../reset/stericsson,db8500-prcc-reset.h | 51 +++++++++ 3 files changed, 172 insertions(+), 64 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml delete mode 100644 Documentation/devicetree/bindings/clock/ux500.txt create mode 100644 include/dt-bindings/reset/stericsson,db8500-prcc-reset.h (limited to 'include/dt-bindings/reset') diff --git a/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml b/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml new file mode 100644 index 000000000000..9bc95a308477 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST-Ericsson DB8500 (U8500) clocks + +maintainers: + - Ulf Hansson + - Linus Walleij + +description: While named "U8500 clocks" these clocks are inside the + DB8500 digital baseband system-on-chip and its siblings such as + DB8520. These bindings consider the clocks present in the SoC + itself, not off-chip clocks. There are four different on-chip + clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and + control management unit) clocks and PRCC (peripheral reset and + clock controller) clocks. For some reason PRCC 4 does not exist so + the itemization can be a bit unintuitive. + +properties: + compatible: + enum: + - stericsson,u8500-clks + - stericsson,u8540-clks + - stericsson,u9540-clks + + reg: + items: + - description: PRCC 1 register area + - description: PRCC 2 register area + - description: PRCC 3 register area + - description: PRCC 5 register area + - description: PRCC 6 register area + + prcmu-clock: + description: A subnode with one clock cell for PRCMU (power, reset, control + management unit) clocks. The cell indicates which PRCMU clock in the + prcmu-clock node the consumer wants to use. + type: object + + properties: + '#clock-cells': + const: 1 + + additionalProperties: false + + prcc-periph-clock: + description: A subnode with two clock cells for PRCC (peripheral + reset and clock controller) peripheral clocks. The first cell indicates + which PRCC block the consumer wants to use, possible values are 1, 2, 3, + 5, 6. The second cell indicates which clock inside the PRCC block it + wants, possible values are 0 thru 31. + type: object + + properties: + '#clock-cells': + const: 2 + + additionalProperties: false + + prcc-kernel-clock: + description: A subnode with two clock cells for PRCC (peripheral reset + and clock controller) kernel clocks. The first cell indicates which PRCC + block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The + second cell indicates which clock inside the PRCC block it wants, possible + values are 0 thru 31. + type: object + + properties: + '#clock-cells': + const: 2 + + additionalProperties: false + + prcc-reset-controller: + description: A subnode with two reset cells for the reset portions of the + PRCC (peripheral reset and clock controller). The first cell indicates + which PRCC block the consumer wants to use, possible values are 1, 2, 3 + 5 and 6. The second cell indicates which reset line inside the PRCC block + it wants to control, possible values are 0 thru 31. + type: object + + properties: + '#reset-cells': + const: 2 + + additionalProperties: false + + rtc32k-clock: + description: A subnode with zero clock cells for the 32kHz RTC clock. + type: object + + properties: + '#clock-cells': + const: 0 + + additionalProperties: false + + smp-twd-clock: + description: A subnode for the ARM SMP Timer Watchdog cluster with zero + clock cells. + type: object + + properties: + '#clock-cells': + const: 0 + + additionalProperties: false + +required: + - compatible + - reg + - prcmu-clock + - prcc-periph-clock + - prcc-kernel-clock + - rtc32k-clock + - smp-twd-clock + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/ux500.txt b/Documentation/devicetree/bindings/clock/ux500.txt deleted file mode 100644 index e52bd4b72348..000000000000 --- a/Documentation/devicetree/bindings/clock/ux500.txt +++ /dev/null @@ -1,64 +0,0 @@ -Clock bindings for ST-Ericsson Ux500 clocks - -Required properties : -- compatible : shall contain only one of the following: - "stericsson,u8500-clks" - "stericsson,u8540-clks" - "stericsson,u9540-clks" -- reg : shall contain base register location and length for - CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of - CLKRST4, which does not exist. - -Required subnodes: -- prcmu-clock: a subnode with one clock cell for PRCMU (power, - reset, control unit) clocks. The cell indicates which PRCMU - clock in the prcmu-clock node the consumer wants to use. -- prcc-periph-clock: a subnode with two clock cells for - PRCC (programmable reset- and clock controller) peripheral clocks. - The first cell indicates which PRCC block the consumer - wants to use, possible values are 1, 2, 3, 5, 6. The second - cell indicates which clock inside the PRCC block it wants, - possible values are 0 thru 31. -- prcc-kernel-clock: a subnode with two clock cells for - PRCC (programmable reset- and clock controller) kernel clocks - The first cell indicates which PRCC block the consumer - wants to use, possible values are 1, 2, 3, 5, 6. The second - cell indicates which clock inside the PRCC block it wants, - possible values are 0 thru 31. -- rtc32k-clock: a subnode with zero clock cells for the 32kHz - RTC clock. -- smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster - with zero clock cells. - -Example: - -clocks { - compatible = "stericsson,u8500-clks"; - /* - * Registers for the CLKRST block on peripheral - * groups 1, 2, 3, 5, 6, - */ - reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, - <0x8000f000 0x1000>, <0xa03ff000 0x1000>, - <0xa03cf000 0x1000>; - - prcmu_clk: prcmu-clock { - #clock-cells = <1>; - }; - - prcc_pclk: prcc-periph-clock { - #clock-cells = <2>; - }; - - prcc_kclk: prcc-kernel-clock { - #clock-cells = <2>; - }; - - rtc_clk: rtc32k-clock { - #clock-cells = <0>; - }; - - smp_twd_clk: smp-twd-clock { - #clock-cells = <0>; - }; -}; diff --git a/include/dt-bindings/reset/stericsson,db8500-prcc-reset.h b/include/dt-bindings/reset/stericsson,db8500-prcc-reset.h new file mode 100644 index 000000000000..ea906896c70f --- /dev/null +++ b/include/dt-bindings/reset/stericsson,db8500-prcc-reset.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_STE_PRCC_RESET +#define _DT_BINDINGS_STE_PRCC_RESET + +#define DB8500_PRCC_1 1 +#define DB8500_PRCC_2 2 +#define DB8500_PRCC_3 3 +#define DB8500_PRCC_6 6 + +/* Reset lines on PRCC 1 */ +#define DB8500_PRCC_1_RESET_UART0 0 +#define DB8500_PRCC_1_RESET_UART1 1 +#define DB8500_PRCC_1_RESET_I2C1 2 +#define DB8500_PRCC_1_RESET_MSP0 3 +#define DB8500_PRCC_1_RESET_MSP1 4 +#define DB8500_PRCC_1_RESET_SDI0 5 +#define DB8500_PRCC_1_RESET_I2C2 6 +#define DB8500_PRCC_1_RESET_SPI3 7 +#define DB8500_PRCC_1_RESET_SLIMBUS0 8 +#define DB8500_PRCC_1_RESET_I2C4 9 +#define DB8500_PRCC_1_RESET_MSP3 10 +#define DB8500_PRCC_1_RESET_PER_MSP3 11 +#define DB8500_PRCC_1_RESET_PER_MSP1 12 +#define DB8500_PRCC_1_RESET_PER_MSP0 13 +#define DB8500_PRCC_1_RESET_PER_SLIMBUS 14 + +/* Reset lines on PRCC 2 */ +#define DB8500_PRCC_2_RESET_I2C3 0 +#define DB8500_PRCC_2_RESET_PWL 1 +#define DB8500_PRCC_2_RESET_SDI4 2 +#define DB8500_PRCC_2_RESET_MSP2 3 +#define DB8500_PRCC_2_RESET_SDI1 4 +#define DB8500_PRCC_2_RESET_SDI3 5 +#define DB8500_PRCC_2_RESET_HSIRX 6 +#define DB8500_PRCC_2_RESET_HSITX 7 +#define DB8500_PRCC_1_RESET_PER_MSP2 8 + +/* Reset lines on PRCC 3 */ +#define DB8500_PRCC_3_RESET_SSP0 1 +#define DB8500_PRCC_3_RESET_SSP1 2 +#define DB8500_PRCC_3_RESET_I2C0 3 +#define DB8500_PRCC_3_RESET_SDI2 4 +#define DB8500_PRCC_3_RESET_SKE 5 +#define DB8500_PRCC_3_RESET_UART2 6 +#define DB8500_PRCC_3_RESET_SDI5 7 + +/* Reset lines on PRCC 6 */ +#define DB8500_PRCC_3_RESET_RNG 0 + +#endif -- cgit v1.2.3