From bcde37225438687231bb9510c07e60dcb8db1988 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 10 Jun 2014 23:53:27 -0700 Subject: ARM: shmobile: r8a7790: add MSTP10 support on DTSI Signed-off-by: Kuninori Morimoto Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- include/dt-bindings/clock/r8a7790-clock.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index 1118f7a4bca6..a16df68ac97d 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -107,4 +107,30 @@ #define R8A7790_CLK_I2C1 30 #define R8A7790_CLK_I2C0 31 +/* MSTP10 */ +#define R8A7790_CLK_SSI_ALL 5 +#define R8A7790_CLK_SSI9 6 +#define R8A7790_CLK_SSI8 7 +#define R8A7790_CLK_SSI7 8 +#define R8A7790_CLK_SSI6 9 +#define R8A7790_CLK_SSI5 10 +#define R8A7790_CLK_SSI4 11 +#define R8A7790_CLK_SSI3 12 +#define R8A7790_CLK_SSI2 13 +#define R8A7790_CLK_SSI1 14 +#define R8A7790_CLK_SSI0 15 +#define R8A7790_CLK_SCU_ALL 17 +#define R8A7790_CLK_SCU_DVC1 18 +#define R8A7790_CLK_SCU_DVC0 19 +#define R8A7790_CLK_SCU_SRC9 22 +#define R8A7790_CLK_SCU_SRC8 23 +#define R8A7790_CLK_SCU_SRC7 24 +#define R8A7790_CLK_SCU_SRC6 25 +#define R8A7790_CLK_SCU_SRC5 26 +#define R8A7790_CLK_SCU_SRC4 27 +#define R8A7790_CLK_SCU_SRC3 28 +#define R8A7790_CLK_SCU_SRC2 29 +#define R8A7790_CLK_SCU_SRC1 30 +#define R8A7790_CLK_SCU_SRC0 31 + #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ -- cgit v1.2.3 From ee9141522dcf13f861ed3cef6490c6cbfaafefb9 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 11 Jun 2014 21:44:16 -0700 Subject: ARM: shmobile: r8a7791: add MSTP10 support on DTSI Signed-off-by: Kuninori Morimoto Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 33 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/r8a7791-clock.h | 26 ++++++++++++++++++++++++ 2 files changed, 59 insertions(+) (limited to 'include/dt-bindings') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f3b6219cc09e..380d058e4210 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -865,6 +865,39 @@ "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; + + #clock-cells = <1>; + clock-indices = < + R8A7791_CLK_SSI_ALL + R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 + R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 + R8A7791_CLK_SCU_ALL + R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 + R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 + R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 + >; + clock-output-names = + "ssi-all", + "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", + "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", + "scu-all", + "scu-dvc1", "scu-dvc0", + "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", + "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; + }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index b050d18437ce..0410bea2ad1d 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -107,6 +107,32 @@ #define R8A7791_CLK_I2C1 30 #define R8A7791_CLK_I2C0 31 +/* MSTP10 */ +#define R8A7791_CLK_SSI_ALL 5 +#define R8A7791_CLK_SSI9 6 +#define R8A7791_CLK_SSI8 7 +#define R8A7791_CLK_SSI7 8 +#define R8A7791_CLK_SSI6 9 +#define R8A7791_CLK_SSI5 10 +#define R8A7791_CLK_SSI4 11 +#define R8A7791_CLK_SSI3 12 +#define R8A7791_CLK_SSI2 13 +#define R8A7791_CLK_SSI1 14 +#define R8A7791_CLK_SSI0 15 +#define R8A7791_CLK_SCU_ALL 17 +#define R8A7791_CLK_SCU_DVC1 18 +#define R8A7791_CLK_SCU_DVC0 19 +#define R8A7791_CLK_SCU_SRC9 22 +#define R8A7791_CLK_SCU_SRC8 23 +#define R8A7791_CLK_SCU_SRC7 24 +#define R8A7791_CLK_SCU_SRC6 25 +#define R8A7791_CLK_SCU_SRC5 26 +#define R8A7791_CLK_SCU_SRC4 27 +#define R8A7791_CLK_SCU_SRC3 28 +#define R8A7791_CLK_SCU_SRC2 29 +#define R8A7791_CLK_SCU_SRC1 30 +#define R8A7791_CLK_SCU_SRC0 31 + /* MSTP11 */ #define R8A7791_CLK_SCIFA3 6 #define R8A7791_CLK_SCIFA4 7 -- cgit v1.2.3 From ecafea8cd261833d7bb857aad76cf2e721821e88 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:15 +0100 Subject: ARM: shmobile: r8a7790: Add PCIEC clock device tree node This patch adds the device tree clock node for the PCIe Controller Signed-off-by: Phil Edworthy Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 6 +++--- include/dt-bindings/clock/r8a7790-clock.h | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'include/dt-bindings') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 29907c9d8e5b..9df57122e9c0 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -765,17 +765,17 @@ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; + <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 - R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 + R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 >; clock-output-names = "iic2", "tpu0", "mmcif1", "sdhi3", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "iic1", "ssusb", "cmt1"; + "iic0", "pciec", "iic1", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index a16df68ac97d..f929a79e6998 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -59,6 +59,7 @@ #define R8A7790_CLK_SDHI0 14 #define R8A7790_CLK_MMCIF0 15 #define R8A7790_CLK_IIC0 18 +#define R8A7790_CLK_PCIEC 19 #define R8A7790_CLK_IIC1 23 #define R8A7790_CLK_SSUSB 28 #define R8A7790_CLK_CMT1 29 -- cgit v1.2.3 From 4bfb37675b5343798f5260adad92a67444a9fd47 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jun 2014 10:37:18 +0100 Subject: ARM: shmobile: r8a7791: Add PCIEC clock device tree node This patch adds the device tree clock node for the PCIe Controller Signed-off-by: Phil Edworthy Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 7 ++++--- include/dt-bindings/clock/r8a7791-clock.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'include/dt-bindings') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 380d058e4210..a15bf7af63e4 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -795,15 +795,16 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; + <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 - R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 + R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 + R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 >; clock-output-names = "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1"; + "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index 0410bea2ad1d..f0d4d1049162 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -53,6 +53,7 @@ #define R8A7791_CLK_SDHI0 14 #define R8A7791_CLK_MMCIF0 15 #define R8A7791_CLK_IIC0 18 +#define R8A7791_CLK_PCIEC 19 #define R8A7791_CLK_IIC1 23 #define R8A7791_CLK_SSUSB 28 #define R8A7791_CLK_CMT1 29 -- cgit v1.2.3