From a9beb0a21c8b740ab611c4385e2c59f5911a4da6 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 28 Aug 2017 00:33:23 +0200 Subject: dt-bindings: add power-domain header for RK3188 SoCs Add rk3188 power-domains as described by the TRM. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- include/dt-bindings/power/rk3188-power.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/dt-bindings/power/rk3188-power.h (limited to 'include') diff --git a/include/dt-bindings/power/rk3188-power.h b/include/dt-bindings/power/rk3188-power.h new file mode 100644 index 000000000000..93d23dfba33f --- /dev/null +++ b/include/dt-bindings/power/rk3188-power.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ +#define __DT_BINDINGS_POWER_RK3188_POWER_H__ + +/* VD_CORE */ +#define RK3188_PD_A9_0 0 +#define RK3188_PD_A9_1 1 +#define RK3188_PD_A9_2 2 +#define RK3188_PD_A9_3 3 +#define RK3188_PD_DBG 4 +#define RK3188_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3188_PD_VIDEO 6 +#define RK3188_PD_VIO 7 +#define RK3188_PD_GPU 8 +#define RK3188_PD_PERI 9 +#define RK3188_PD_CPU 10 +#define RK3188_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3188_PD_RTC 12 + +#endif -- cgit v1.2.3 From 2e99be2874484609ade7d80f688fa8c6dc42759b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 28 Aug 2017 00:36:25 +0200 Subject: dt-bindings: add power-domain header for RK3066 SoCs Add rk3066 power-domains as described by the TRM. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- include/dt-bindings/power/rk3066-power.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 include/dt-bindings/power/rk3066-power.h (limited to 'include') diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h new file mode 100644 index 000000000000..acf9f310ac53 --- /dev/null +++ b/include/dt-bindings/power/rk3066-power.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ +#define __DT_BINDINGS_POWER_RK3066_POWER_H__ + +/* VD_CORE */ +#define RK3066_PD_A9_0 0 +#define RK3066_PD_A9_1 1 +#define RK3066_PD_DBG 4 +#define RK3066_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3066_PD_VIDEO 6 +#define RK3066_PD_VIO 7 +#define RK3066_PD_GPU 8 +#define RK3066_PD_PERI 9 +#define RK3066_PD_CPU 10 +#define RK3066_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3066_PD_RTC 12 + +#endif -- cgit v1.2.3 From d78b5bde0ffc33d20f014b3ad4d7aaac8b79d34e Mon Sep 17 00:00:00 2001 From: Timo Alho Date: Mon, 22 Oct 2018 16:19:36 +0300 Subject: firmware: tegra: Add helper to check for supported MRQs Add a helper function to check that firmware is supporting a given MRQ command. Signed-off-by: Timo Alho Acked-by: Sivaram Nair Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/firmware/tegra/bpmp.c | 25 +++++++++++++++++++++++++ include/soc/tegra/bpmp.h | 7 +++++++ 2 files changed, 32 insertions(+) (limited to 'include') diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index a3d5b518c10e..90c6089fed84 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -470,6 +470,31 @@ unlock: } EXPORT_SYMBOL_GPL(tegra_bpmp_free_mrq); +bool tegra_bpmp_mrq_is_supported(struct tegra_bpmp *bpmp, unsigned int mrq) +{ + struct mrq_query_abi_request req = { .mrq = cpu_to_le32(mrq) }; + struct mrq_query_abi_response resp; + struct tegra_bpmp_message msg = { + .mrq = MRQ_QUERY_ABI, + .tx = { + .data = &req, + .size = sizeof(req), + }, + .rx = { + .data = &resp, + .size = sizeof(resp), + }, + }; + int ret; + + ret = tegra_bpmp_transfer(bpmp, &msg); + if (ret || msg.rx.ret) + return false; + + return resp.status == 0; +} +EXPORT_SYMBOL_GPL(tegra_bpmp_mrq_is_supported); + static void tegra_bpmp_mrq_handle_ping(unsigned int mrq, struct tegra_bpmp_channel *channel, void *data) diff --git a/include/soc/tegra/bpmp.h b/include/soc/tegra/bpmp.h index e69e4c4d80ae..b02f926a0216 100644 --- a/include/soc/tegra/bpmp.h +++ b/include/soc/tegra/bpmp.h @@ -129,6 +129,7 @@ int tegra_bpmp_request_mrq(struct tegra_bpmp *bpmp, unsigned int mrq, tegra_bpmp_mrq_handler_t handler, void *data); void tegra_bpmp_free_mrq(struct tegra_bpmp *bpmp, unsigned int mrq, void *data); +bool tegra_bpmp_mrq_is_supported(struct tegra_bpmp *bpmp, unsigned int mrq); #else static inline struct tegra_bpmp *tegra_bpmp_get(struct device *dev) { @@ -164,6 +165,12 @@ static inline void tegra_bpmp_free_mrq(struct tegra_bpmp *bpmp, unsigned int mrq, void *data) { } + +static inline bool tegra_bpmp_mrq_is_supported(struct tegra_bpmp *bpmp, + unsigned int mrq) +{ + return false; +} #endif #if IS_ENABLED(CONFIG_CLK_TEGRA_BPMP) -- cgit v1.2.3 From 4bef358c9071748aa3e55f70f3ba5abc6363fcfe Mon Sep 17 00:00:00 2001 From: Timo Alho Date: Mon, 22 Oct 2018 16:19:39 +0300 Subject: soc/tegra: bpmp: Update ABI header Update the firmware header file to a more recent version. The major changes in the new version are: * add a new MRQ for firmware version query ABI and deprecates the old * add ABI to query Tegra194 CPU frequency limits * add ABI to control subset of PCIE UPHY state The new header contains also some editorial changes to the documentation. Signed-off-by: Timo Alho Acked-by: Sivaram Nair Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- include/soc/tegra/bpmp-abi.h | 1188 +++++++++++++++++++++++++++++++++--------- 1 file changed, 947 insertions(+), 241 deletions(-) (limited to 'include') diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h index 98d8d38b99a1..ab7f8796a260 100644 --- a/include/soc/tegra/bpmp-abi.h +++ b/include/soc/tegra/bpmp-abi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -40,7 +40,6 @@ * @file */ - /** * @defgroup MRQ MRQ Messages * @brief Messages sent to/from BPMP via IPC @@ -53,7 +52,7 @@ */ /** - * @addtogroup MRQ_Format Message Format + * @addtogroup MRQ_Format * @{ * The CPU requests the BPMP to perform a particular service by * sending it an IVC frame containing a single MRQ message. An MRQ @@ -76,7 +75,7 @@ /** * @ingroup MRQ_Format - * @brief header for an MRQ message + * @brief Header for an MRQ message * * Provides the MRQ number for the MRQ message: #mrq. The remainder of * the MRQ message is a payload (immediately following the @@ -86,7 +85,7 @@ struct mrq_request { /** @brief MRQ number of the request */ uint32_t mrq; /** - * @brief flags providing follow up directions to the receiver + * @brief Flags providing follow up directions to the receiver * * | Bit | Description | * |-----|--------------------------------------------| @@ -98,7 +97,7 @@ struct mrq_request { /** * @ingroup MRQ_Format - * @brief header for an MRQ response + * @brief Header for an MRQ response * * Provides an error code for the associated MRQ message. The * remainder of the MRQ response is a payload (immediately following @@ -106,9 +105,9 @@ struct mrq_request { * mrq_request::mrq */ struct mrq_response { - /** @brief error code for the MRQ request itself */ + /** @brief Error code for the MRQ request itself */ int32_t err; - /** @brief reserved for future use */ + /** @brief Reserved for future use */ uint32_t flags; } __ABI_PACKED; @@ -152,6 +151,14 @@ struct mrq_response { #define MRQ_TRACE_ITER 64 #define MRQ_RINGBUF_CONSOLE 65 #define MRQ_PG 66 +#define MRQ_CPU_NDIV_LIMITS 67 +#define MRQ_STRAP 68 +#define MRQ_UPHY 69 +#define MRQ_CPU_AUTO_CC3 70 +#define MRQ_QUERY_FW_TAG 71 +#define MRQ_FMON 72 +#define MRQ_EC 73 +#define MRQ_FBVOLT_STATUS 74 /** @} */ @@ -160,31 +167,35 @@ struct mrq_response { * @brief Maximum MRQ code to be sent by CPU software to * BPMP. Subject to change in future */ -#define MAX_CPU_MRQ_ID 66 +#define MAX_CPU_MRQ_ID 74 /** - * @addtogroup MRQ_Payloads Message Payloads + * @addtogroup MRQ_Payloads * @{ - * @defgroup Ping + * @defgroup Ping Ping * @defgroup Query_Tag Query Tag * @defgroup Module Loadable Modules - * @defgroup Trace - * @defgroup Debugfs - * @defgroup Reset - * @defgroup I2C - * @defgroup Clocks + * @defgroup Trace Trace + * @defgroup Debugfs Debug File System + * @defgroup Reset Reset + * @defgroup I2C I2C + * @defgroup Clocks Clocks * @defgroup ABI_info ABI Info - * @defgroup MC_Flush MC Flush - * @defgroup Powergating - * @defgroup Thermal + * @defgroup Powergating Power Gating + * @defgroup Thermal Thermal * @defgroup Vhint CPU Voltage hint - * @defgroup MRQ_Deprecated Deprecated MRQ messages - * @defgroup EMC - * @defgroup RingbufConsole + * @defgroup EMC EMC + * @defgroup CPU NDIV Limits + * @defgroup RingbufConsole Ring Buffer Console + * @defgroup Strap Straps + * @defgroup UPHY UPHY + * @defgroup CC3 Auto-CC3 + * @defgroup FMON FMON + * @defgroup EC EC + * @defgroup Fbvolt_status Fuse Burn Voltage Status * @} */ - /** * @ingroup MRQ_Codes * @def MRQ_PING @@ -214,20 +225,20 @@ struct mrq_response { /** * @ingroup Ping - * @brief request with #MRQ_PING + * @brief Request with #MRQ_PING * * Used by the sender of an #MRQ_PING message to request a pong from * recipient. The response from the recipient is computed based on * #challenge. */ struct mrq_ping_request { -/** @brief arbitrarily chosen value */ +/** @brief Arbitrarily chosen value */ uint32_t challenge; } __ABI_PACKED; /** * @ingroup Ping - * @brief response to #MRQ_PING + * @brief Response to #MRQ_PING * * Sent in response to an #MRQ_PING message. #reply should be the * mrq_ping_request challenge left shifted by 1 with the carry-bit @@ -235,14 +246,16 @@ struct mrq_ping_request { * */ struct mrq_ping_response { - /** @brief response to the MRQ_PING challege */ + /** @brief Response to the MRQ_PING challege */ uint32_t reply; } __ABI_PACKED; /** * @ingroup MRQ_Codes * @def MRQ_QUERY_TAG - * @brief Query BPMP firmware's tag (i.e. version information) + * @brief Query BPMP firmware's tag (i.e. unique identifer) + * + * @deprecated Use #MRQ_QUERY_FW_TAG instead. * * * Platforms: All * * Initiators: CCPLEX @@ -254,25 +267,50 @@ struct mrq_ping_response { /** * @ingroup Query_Tag - * @brief request with #MRQ_QUERY_TAG - * - * Used by #MRQ_QUERY_TAG call to ask BPMP to fill in the memory - * pointed by #addr with BPMP firmware header. + * @brief Request with #MRQ_QUERY_TAG * - * The sender is reponsible for ensuring that #addr is mapped in to - * the recipient's address map. + * @deprecated This structure will be removed in future version. + * Use MRQ_QUERY_FW_TAG instead. */ struct mrq_query_tag_request { - /** @brief base address to store the firmware header */ + /** @brief Base address to store the firmware tag */ uint32_t addr; } __ABI_PACKED; + /** * @ingroup MRQ_Codes - * @def MRQ_MODULE_LOAD - * @brief dynamically load a BPMP code module + * @def MRQ_QUERY_FW_TAG + * @brief Query BPMP firmware's tag (i.e. unique identifier) * * * Platforms: All + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_query_fw_tag_response + * + */ + +/** + * @ingroup Query_Tag + * @brief Response to #MRQ_QUERY_FW_TAG + * + * Sent in response to #MRQ_QUERY_FW_TAG message. #tag contains the unique + * identifier for the version of firmware issuing the reply. + * + */ +struct mrq_query_fw_tag_response { + /** @brief Array to store tag information */ + uint8_t tag[32]; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_LOAD + * @brief Dynamically load a BPMP code module + * + * * Platforms: T210, T214, T186 + * @cond (bpmp_t210 || bpmp_t214 || bpmp_t186) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_module_load_request @@ -284,7 +322,7 @@ struct mrq_query_tag_request { /** * @ingroup Module - * @brief request with #MRQ_MODULE_LOAD + * @brief Request with #MRQ_MODULE_LOAD * * Used by #MRQ_MODULE_LOAD calls to ask the recipient to dynamically * load the code located at #phys_addr and having size #size @@ -300,29 +338,31 @@ struct mrq_query_tag_request { * */ struct mrq_module_load_request { - /** @brief base address of the code to load. Treated as (void *) */ + /** @brief Base address of the code to load. Treated as (void *) */ uint32_t phys_addr; /* (void *) */ - /** @brief size in bytes of code to load */ + /** @brief Size in bytes of code to load */ uint32_t size; } __ABI_PACKED; /** * @ingroup Module - * @brief response to #MRQ_MODULE_LOAD + * @brief Response to #MRQ_MODULE_LOAD * * @todo document mrq_response::err */ struct mrq_module_load_response { - /** @brief handle to the loaded module */ + /** @brief Handle to the loaded module */ uint32_t base; } __ABI_PACKED; +/** @endcond*/ /** * @ingroup MRQ_Codes * @def MRQ_MODULE_UNLOAD - * @brief unload a previously loaded code module + * @brief Unload a previously loaded code module * - * * Platforms: All + * * Platforms: T210, T214, T186 + * @cond (bpmp_t210 || bpmp_t214 || bpmp_t186) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_module_unload_request @@ -333,20 +373,21 @@ struct mrq_module_load_response { /** * @ingroup Module - * @brief request with #MRQ_MODULE_UNLOAD + * @brief Request with #MRQ_MODULE_UNLOAD * * Used by #MRQ_MODULE_UNLOAD calls to request that a previously loaded * module be unloaded. */ struct mrq_module_unload_request { - /** @brief handle of the module to unload */ + /** @brief Handle of the module to unload */ uint32_t base; } __ABI_PACKED; +/** @endcond*/ /** * @ingroup MRQ_Codes * @def MRQ_TRACE_MODIFY - * @brief modify the set of enabled trace events + * @brief Modify the set of enabled trace events * * * Platforms: All * * Initiators: CCPLEX @@ -359,22 +400,22 @@ struct mrq_module_unload_request { /** * @ingroup Trace - * @brief request with #MRQ_TRACE_MODIFY + * @brief Request with #MRQ_TRACE_MODIFY * * Used by %MRQ_TRACE_MODIFY calls to enable or disable specify trace * events. #set takes precedence for any bit set in both #set and * #clr. */ struct mrq_trace_modify_request { - /** @brief bit mask of trace events to disable */ + /** @brief Bit mask of trace events to disable */ uint32_t clr; - /** @brief bit mask of trace events to enable */ + /** @brief Bit mask of trace events to enable */ uint32_t set; } __ABI_PACKED; /** * @ingroup Trace - * @brief response to #MRQ_TRACE_MODIFY + * @brief Response to #MRQ_TRACE_MODIFY * * Sent in repsonse to an #MRQ_TRACE_MODIFY message. #mask reflects the * state of which events are enabled after the recipient acted on the @@ -382,7 +423,7 @@ struct mrq_trace_modify_request { * */ struct mrq_trace_modify_response { - /** @brief bit mask of trace event enable states */ + /** @brief Bit mask of trace event enable states */ uint32_t mask; } __ABI_PACKED; @@ -407,7 +448,7 @@ struct mrq_trace_modify_response { /** * @ingroup Trace - * @brief request with #MRQ_WRITE_TRACE + * @brief Request with #MRQ_WRITE_TRACE * * Used by MRQ_WRITE_TRACE calls to ask the recipient to copy trace * data from the recipient's local buffer to the output buffer. #area @@ -420,22 +461,22 @@ struct mrq_trace_modify_response { * overwrites. */ struct mrq_write_trace_request { - /** @brief base address of output buffer */ + /** @brief Base address of output buffer */ uint32_t area; - /** @brief size in bytes of the output buffer */ + /** @brief Size in bytes of the output buffer */ uint32_t size; } __ABI_PACKED; /** * @ingroup Trace - * @brief response to #MRQ_WRITE_TRACE + * @brief Response to #MRQ_WRITE_TRACE * * Once this response is sent, the respondent will not access the * output buffer further. */ struct mrq_write_trace_response { /** - * @brief flag whether more data remains in local buffer + * @brief Flag whether more data remains in local buffer * * Value is 1 if the entire local trace buffer has been * drained to the outputbuffer. Value is 0 otherwise. @@ -456,9 +497,10 @@ struct mrq_threaded_ping_response { /** * @ingroup MRQ_Codes * @def MRQ_MODULE_MAIL - * @brief send a message to a loadable module + * @brief Send a message to a loadable module * - * * Platforms: All + * * Platforms: T210, T214, T186 + * @cond (bpmp_t210 || bpmp_t214 || bpmp_t186) * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_module_mail_request @@ -469,12 +511,12 @@ struct mrq_threaded_ping_response { /** * @ingroup Module - * @brief request with #MRQ_MODULE_MAIL + * @brief Request with #MRQ_MODULE_MAIL */ struct mrq_module_mail_request { - /** @brief handle to the previously loaded module */ + /** @brief Handle to the previously loaded module */ uint32_t base; - /** @brief module-specific mail payload + /** @brief Module-specific mail payload * * The length of data[ ] is unknown to the BPMP core firmware * but it is limited to the size of an IPC message. @@ -484,23 +526,24 @@ struct mrq_module_mail_request { /** * @ingroup Module - * @brief response to #MRQ_MODULE_MAIL + * @brief Response to #MRQ_MODULE_MAIL */ struct mrq_module_mail_response { - /** @brief module-specific mail payload + /** @brief Module-specific mail payload * * The length of data[ ] is unknown to the BPMP core firmware * but it is limited to the size of an IPC message. */ uint8_t data[EMPTY_ARRAY]; } __ABI_PACKED; +/** @endcond */ /** * @ingroup MRQ_Codes * @def MRQ_DEBUGFS * @brief Interact with BPMP's debugfs file nodes * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_debugfs_request @@ -529,65 +572,70 @@ struct mrq_module_mail_response { * * @} */ + /** @ingroup Debugfs */ enum mrq_debugfs_commands { + /** @brief Perform read */ CMD_DEBUGFS_READ = 1, + /** @brief Perform write */ CMD_DEBUGFS_WRITE = 2, + /** @brief Perform dumping directory */ CMD_DEBUGFS_DUMPDIR = 3, + /** @brief Not a command */ CMD_DEBUGFS_MAX }; /** * @ingroup Debugfs - * @brief parameters for CMD_DEBUGFS_READ/WRITE command + * @brief Parameters for CMD_DEBUGFS_READ/WRITE command */ struct cmd_debugfs_fileop_request { - /** @brief physical address pointing at filename */ + /** @brief Physical address pointing at filename */ uint32_t fnameaddr; - /** @brief length in bytes of filename buffer */ + /** @brief Length in bytes of filename buffer */ uint32_t fnamelen; - /** @brief physical address pointing to data buffer */ + /** @brief Physical address pointing to data buffer */ uint32_t dataaddr; - /** @brief length in bytes of data buffer */ + /** @brief Length in bytes of data buffer */ uint32_t datalen; } __ABI_PACKED; /** * @ingroup Debugfs - * @brief parameters for CMD_DEBUGFS_READ/WRITE command + * @brief Parameters for CMD_DEBUGFS_READ/WRITE command */ struct cmd_debugfs_dumpdir_request { - /** @brief physical address pointing to data buffer */ + /** @brief Physical address pointing to data buffer */ uint32_t dataaddr; - /** @brief length in bytes of data buffer */ + /** @brief Length in bytes of data buffer */ uint32_t datalen; } __ABI_PACKED; /** * @ingroup Debugfs - * @brief response data for CMD_DEBUGFS_READ/WRITE command + * @brief Response data for CMD_DEBUGFS_READ/WRITE command */ struct cmd_debugfs_fileop_response { - /** @brief always 0 */ + /** @brief Always 0 */ uint32_t reserved; - /** @brief number of bytes read from or written to data buffer */ + /** @brief Number of bytes read from or written to data buffer */ uint32_t nbytes; } __ABI_PACKED; /** * @ingroup Debugfs - * @brief response data for CMD_DEBUGFS_DUMPDIR command + * @brief Response data for CMD_DEBUGFS_DUMPDIR command */ struct cmd_debugfs_dumpdir_response { - /** @brief always 0 */ + /** @brief Always 0 */ uint32_t reserved; - /** @brief number of bytes read from or written to data buffer */ + /** @brief Number of bytes read from or written to data buffer */ uint32_t nbytes; } __ABI_PACKED; /** * @ingroup Debugfs - * @brief request with #MRQ_DEBUGFS. + * @brief Request with #MRQ_DEBUGFS. * * The sender of an MRQ_DEBUGFS message uses #cmd to specify a debugfs * command to execute. Legal commands are the values of @ref @@ -601,6 +649,7 @@ struct cmd_debugfs_dumpdir_response { * |CMD_DEBUGFS_DUMPDIR|dumpdir| */ struct mrq_debugfs_request { + /** @brief Sub-command (@ref mrq_debugfs_commands) */ uint32_t cmd; union { struct cmd_debugfs_fileop_request fop; @@ -612,14 +661,14 @@ struct mrq_debugfs_request { * @ingroup Debugfs */ struct mrq_debugfs_response { - /** @brief always 0 */ + /** @brief Always 0 */ int32_t reserved; union { - /** @brief response data for CMD_DEBUGFS_READ OR + /** @brief Response data for CMD_DEBUGFS_READ OR * CMD_DEBUGFS_WRITE command */ struct cmd_debugfs_fileop_response fop; - /** @brief response data for CMD_DEBUGFS_DUMPDIR command */ + /** @brief Response data for CMD_DEBUGFS_DUMPDIR command */ struct cmd_debugfs_dumpdir_response dumpdir; } __UNION_ANON; } __ABI_PACKED; @@ -633,57 +682,58 @@ struct mrq_debugfs_response { #define DEBUGFS_S_IWUSR (1 << 7) /** @} */ - /** * @ingroup MRQ_Codes * @def MRQ_RESET - * @brief reset an IP block + * @brief Reset an IP block * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_reset_request * * Response Payload: @ref mrq_reset_response + * + * @addtogroup Reset + * @{ */ -/** - * @ingroup Reset - */ enum mrq_reset_commands { + /** @brief Assert module reset */ CMD_RESET_ASSERT = 1, + /** @brief Deassert module reset */ CMD_RESET_DEASSERT = 2, + /** @brief Assert and deassert the module reset */ CMD_RESET_MODULE = 3, + /** @brief Get the highest reset ID */ CMD_RESET_GET_MAX_ID = 4, - CMD_RESET_MAX, /* not part of ABI and subject to change */ + /** @brief Not part of ABI and subject to change */ + CMD_RESET_MAX, }; /** - * @ingroup Reset - * @brief request with MRQ_RESET + * @brief Request with MRQ_RESET * * Used by the sender of an #MRQ_RESET message to request BPMP to * assert or or deassert a given reset line. */ struct mrq_reset_request { - /** @brief reset action to perform (@enum mrq_reset_commands) */ + /** @brief Reset action to perform (@ref mrq_reset_commands) */ uint32_t cmd; - /** @brief id of the reset to affected */ + /** @brief Id of the reset to affected */ uint32_t reset_id; } __ABI_PACKED; /** - * @ingroup Reset * @brief Response for MRQ_RESET sub-command CMD_RESET_GET_MAX_ID. When * this sub-command is not supported, firmware will return -BPMP_EBADCMD * in mrq_response::err. */ struct cmd_reset_get_max_id_response { - /** @brief max reset id */ + /** @brief Max reset id */ uint32_t max_id; } __ABI_PACKED; /** - * @ingroup Reset * @brief Response with MRQ_RESET * * Each sub-command supported by @ref mrq_reset_request may return @@ -703,32 +753,25 @@ struct mrq_reset_response { } __UNION_ANON; } __ABI_PACKED; +/** @} */ + /** * @ingroup MRQ_Codes * @def MRQ_I2C - * @brief issue an i2c transaction + * @brief Issue an i2c transaction * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_i2c_request * * Response Payload: @ref mrq_i2c_response - */ - -/** + * * @addtogroup I2C * @{ */ #define TEGRA_I2C_IPC_MAX_IN_BUF_SIZE (MSG_DATA_MIN_SZ - 12) #define TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE (MSG_DATA_MIN_SZ - 4) -/** @} */ -/** - * @ingroup I2C - * @name Serial I2C flags - * Use these flags with serial_i2c_request::flags - * @{ - */ #define SERIALI2C_TEN 0x0010 #define SERIALI2C_RD 0x0001 #define SERIALI2C_STOP 0x8000 @@ -737,15 +780,13 @@ struct mrq_reset_response { #define SERIALI2C_IGNORE_NAK 0x1000 #define SERIALI2C_NO_RD_ACK 0x0800 #define SERIALI2C_RECV_LEN 0x0400 -/** @} */ -/** @ingroup I2C */ + enum { CMD_I2C_XFER = 1 }; /** - * @ingroup I2C - * @brief serializable i2c request + * @brief Serializable i2c request * * Instances of this structure are packed (little-endian) into * cmd_i2c_xfer_request::data_buf. Each instance represents a single @@ -762,80 +803,75 @@ enum { struct serial_i2c_request { /** @brief I2C slave address */ uint16_t addr; - /** @brief bitmask of SERIALI2C_ flags */ + /** @brief Bitmask of SERIALI2C_ flags */ uint16_t flags; - /** @brief length of I2C transaction in bytes */ + /** @brief Length of I2C transaction in bytes */ uint16_t len; - /** @brief for write transactions only, #len bytes of data */ + /** @brief For write transactions only, #len bytes of data */ uint8_t data[]; } __ABI_PACKED; /** - * @ingroup I2C - * @brief trigger one or more i2c transactions + * @brief Trigger one or more i2c transactions */ struct cmd_i2c_xfer_request { - /** @brief valid bus number from mach-t186/i2c-t186.h*/ + /** @brief Valid bus number from @ref bpmp_i2c_ids*/ uint32_t bus_id; - /** @brief count of valid bytes in #data_buf*/ + /** @brief Count of valid bytes in #data_buf*/ uint32_t data_size; - /** @brief serialized packed instances of @ref serial_i2c_request*/ + /** @brief Serialized packed instances of @ref serial_i2c_request*/ uint8_t data_buf[TEGRA_I2C_IPC_MAX_IN_BUF_SIZE]; } __ABI_PACKED; /** - * @ingroup I2C - * @brief container for data read from the i2c bus + * @brief Container for data read from the i2c bus * * Processing an cmd_i2c_xfer_request::data_buf causes BPMP to execute * zero or more I2C reads. The data read from the bus is serialized * into #data_buf. */ struct cmd_i2c_xfer_response { - /** @brief count of valid bytes in #data_buf*/ + /** @brief Count of valid bytes in #data_buf*/ uint32_t data_size; - /** @brief i2c read data */ + /** @brief I2c read data */ uint8_t data_buf[TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE]; } __ABI_PACKED; /** - * @ingroup I2C - * @brief request with #MRQ_I2C + * @brief Request with #MRQ_I2C */ struct mrq_i2c_request { - /** @brief always CMD_I2C_XFER (i.e. 1) */ + /** @brief Always CMD_I2C_XFER (i.e. 1) */ uint32_t cmd; - /** @brief parameters of the transfer request */ + /** @brief Parameters of the transfer request */ struct cmd_i2c_xfer_request xfer; } __ABI_PACKED; /** - * @ingroup I2C - * @brief response to #MRQ_I2C + * @brief Response to #MRQ_I2C */ struct mrq_i2c_response { struct cmd_i2c_xfer_response xfer; } __ABI_PACKED; +/** @} */ + /** * @ingroup MRQ_Codes * @def MRQ_CLK + * @brief Perform a clock operation * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_clk_request * * Response Payload: @ref mrq_clk_response + * * @addtogroup Clocks * @{ */ - -/** - * @name MRQ_CLK sub-commands - * @{ - */ enum { CMD_CLK_GET_RATE = 1, CMD_CLK_SET_RATE = 2, @@ -847,20 +883,13 @@ enum { CMD_CLK_DISABLE = 8, CMD_CLK_GET_ALL_INFO = 14, CMD_CLK_GET_MAX_CLK_ID = 15, + CMD_CLK_GET_FMAX_AT_VMIN = 16, CMD_CLK_MAX, }; -/** @} */ -/** - * @name MRQ_CLK properties - * Flag bits for cmd_clk_properties_response::flags and - * cmd_clk_get_all_info_response::flags - * @{ - */ #define BPMP_CLK_HAS_MUX (1 << 0) #define BPMP_CLK_HAS_SET_RATE (1 << 1) #define BPMP_CLK_IS_ROOT (1 << 2) -/** @} */ #define MRQ_CLK_NAME_MAXLEN 40 #define MRQ_CLK_MAX_PARENTS 16 @@ -959,11 +988,19 @@ struct cmd_clk_get_max_clk_id_request { struct cmd_clk_get_max_clk_id_response { uint32_t max_id; } __ABI_PACKED; -/** @} */ + +/** @private */ +struct cmd_clk_get_fmax_at_vmin_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_fmax_at_vmin_response { + int64_t rate; +} __ABI_PACKED; /** * @ingroup Clocks - * @brief request with #MRQ_CLK + * @brief Request with #MRQ_CLK * * Used by the sender of an #MRQ_CLK message to control clocks. The * clk_request is split into several sub-commands. Some sub-commands @@ -982,11 +1019,13 @@ struct cmd_clk_get_max_clk_id_response { * |CMD_CLK_DISABLE |- | * |CMD_CLK_GET_ALL_INFO |- | * |CMD_CLK_GET_MAX_CLK_ID |- | + * |CMD_CLK_GET_FMAX_AT_VMIN |- + * | * */ struct mrq_clk_request { - /** @brief sub-command and clock id concatenated to 32-bit word. + /** @brief Sub-command and clock id concatenated to 32-bit word. * - bits[31..24] is the sub-cmd. * - bits[23..0] is the clock id */ @@ -1010,12 +1049,14 @@ struct mrq_clk_request { struct cmd_clk_get_all_info_request clk_get_all_info; /** @private */ struct cmd_clk_get_max_clk_id_request clk_get_max_clk_id; + /** @private */ + struct cmd_clk_get_fmax_at_vmin_request clk_get_fmax_at_vmin; } __UNION_ANON; } __ABI_PACKED; /** * @ingroup Clocks - * @brief response to MRQ_CLK + * @brief Response to MRQ_CLK * * Each sub-command supported by @ref mrq_clk_request may return * sub-command-specific data. Some do and some do not as indicated in @@ -1033,6 +1074,7 @@ struct mrq_clk_request { * |CMD_CLK_DISABLE |- | * |CMD_CLK_GET_ALL_INFO |clk_get_all_info | * |CMD_CLK_GET_MAX_CLK_ID |clk_get_max_id | + * |CMD_CLK_GET_FMAX_AT_VMIN |clk_get_fmax_at_vmin | * */ @@ -1050,13 +1092,16 @@ struct mrq_clk_response { struct cmd_clk_is_enabled_response clk_is_enabled; struct cmd_clk_get_all_info_response clk_get_all_info; struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id; + struct cmd_clk_get_fmax_at_vmin_response clk_get_fmax_at_vmin; } __UNION_ANON; } __ABI_PACKED; +/** @} */ + /** * @ingroup MRQ_Codes * @def MRQ_QUERY_ABI - * @brief check if an MRQ is implemented + * @brief Check if an MRQ is implemented * * * Platforms: All * * Initiators: Any @@ -1067,7 +1112,7 @@ struct mrq_clk_response { /** * @ingroup ABI_info - * @brief request with MRQ_QUERY_ABI + * @brief Request with MRQ_QUERY_ABI * * Used by #MRQ_QUERY_ABI call to check if MRQ code #mrq is supported * by the recipient. @@ -1079,7 +1124,7 @@ struct mrq_query_abi_request { /** * @ingroup ABI_info - * @brief response to MRQ_QUERY_ABI + * @brief Response to MRQ_QUERY_ABI * * @note mrq_response::err of 0 indicates that the query was * successful, not that the MRQ itself is supported! @@ -1092,19 +1137,19 @@ struct mrq_query_abi_response { /** * @ingroup MRQ_Codes * @def MRQ_PG_READ_STATE - * @brief read the power-gating state of a partition + * @brief Read the power-gating state of a partition * * * Platforms: T186 + * @cond bpmp_t186 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_pg_read_state_request * * Response Payload: @ref mrq_pg_read_state_response - * @addtogroup Powergating - * @{ */ /** - * @brief request with #MRQ_PG_READ_STATE + * @ingroup Powergating + * @brief Request with #MRQ_PG_READ_STATE * * Used by MRQ_PG_READ_STATE call to read the current state of a * partition. @@ -1115,39 +1160,40 @@ struct mrq_pg_read_state_request { } __ABI_PACKED; /** - * @brief response to MRQ_PG_READ_STATE + * @ingroup Powergating + * @brief Response to MRQ_PG_READ_STATE * @todo define possible errors. */ struct mrq_pg_read_state_response { - /** @brief read as don't care */ + /** @brief Read as don't care */ uint32_t sram_state; - /** @brief state of power partition + /** @brief State of power partition * * 0 : off * * 1 : on */ uint32_t logic_state; } __ABI_PACKED; - +/** @endcond*/ /** @} */ /** * @ingroup MRQ_Codes * @def MRQ_PG_UPDATE_STATE - * @brief modify the power-gating state of a partition. In contrast to + * @brief Modify the power-gating state of a partition. In contrast to * MRQ_PG calls, the operations that change state (on/off) of power * partition are reference counted. * * * Platforms: T186 + * @cond bpmp_t186 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_pg_update_state_request * * Response Payload: N/A - * @addtogroup Powergating - * @{ */ /** - * @brief request with mrq_pg_update_state_request + * @ingroup Powergating + * @brief Request with mrq_pg_update_state_request * * Used by #MRQ_PG_UPDATE_STATE call to request BPMP to change the * state of a power partition #partition_id. @@ -1155,20 +1201,20 @@ struct mrq_pg_read_state_response { struct mrq_pg_update_state_request { /** @brief ID of partition */ uint32_t partition_id; - /** @brief secondary control of power partition + /** @brief Secondary control of power partition * @details Ignored by many versions of the BPMP * firmware. For maximum compatibility, set the value - * according to @logic_state + * according to @ref logic_state * * 0x1: power ON partition (@ref logic_state == 0x3) * * 0x3: power OFF partition (@ref logic_state == 0x1) */ uint32_t sram_state; - /** @brief controls state of power partition, legal values are + /** @brief Controls state of power partition, legal values are * * 0x1 : power OFF partition * * 0x3 : power ON partition */ uint32_t logic_state; - /** @brief change state of clocks of the power partition, legal values + /** @brief Change state of clocks of the power partition, legal values * * 0x0 : do not change clock state * * 0x1 : disable partition clocks (only applicable when * @ref logic_state == 0x1) @@ -1177,7 +1223,7 @@ struct mrq_pg_update_state_request { */ uint32_t clock_state; } __ABI_PACKED; -/** @} */ +/** @endcond*/ /** * @ingroup MRQ_Codes @@ -1186,19 +1232,20 @@ struct mrq_pg_update_state_request { * MRQ_PG_UPDATE_STATE, operations that change the power partition * state are NOT reference counted * - * * Platforms: T186 + * @note BPMP-FW forcefully turns off some partitions as part of SC7 entry + * because their state cannot be adequately restored on exit. Therefore, + * it is recommended to power off all domains via MRQ_PG prior to SC7 entry. + * See @ref bpmp_pdomain_ids for further detail. + * + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_pg_request * * Response Payload: @ref mrq_pg_response + * * @addtogroup Powergating * @{ */ - -/** - * @name MRQ_PG sub-commands - * @{ - */ enum mrq_pg_cmd { /** * @brief Check whether the BPMP driver supports the specified @@ -1232,7 +1279,7 @@ enum mrq_pg_cmd { CMD_PG_GET_STATE = 2, /** - * @brief get the name string of specified power domain id. + * @brief Get the name string of specified power domain id. * * mrq_response:err is * 0: Success @@ -1242,7 +1289,7 @@ enum mrq_pg_cmd { /** - * @brief get the highest power domain id in the system. Not + * @brief Get the highest power domain id in the system. Not * all IDs between 0 and max_id are valid IDs. * * mrq_response:err is @@ -1251,35 +1298,36 @@ enum mrq_pg_cmd { */ CMD_PG_GET_MAX_ID = 4, }; -/** @} */ #define MRQ_PG_NAME_MAXLEN 40 -/** - * @brief possible power domain states in - * cmd_pg_set_state_request:state and cmd_pg_get_state_response:state. - * PG_STATE_OFF: power domain is OFF - * PG_STATE_ON: power domain is ON - * PG_STATE_RUNNING: power domain is ON and made into directly usable - * state by turning on the clocks associated with - * the domain - */ enum pg_states { + /** @brief Power domain is OFF */ PG_STATE_OFF = 0, + /** @brief Power domain is ON */ PG_STATE_ON = 1, + /** + * @brief a legacy state where power domain and the clock + * associated to the domain are ON. + * This state is only supported in T186, and the use of it is + * deprecated. + */ PG_STATE_RUNNING = 2, }; struct cmd_pg_query_abi_request { - uint32_t type; /* enum mrq_pg_cmd */ + /** @ref mrq_pg_cmd */ + uint32_t type; } __ABI_PACKED; struct cmd_pg_set_state_request { - uint32_t state; /* enum pg_states */ + /** @ref pg_states */ + uint32_t state; } __ABI_PACKED; struct cmd_pg_get_state_response { - uint32_t state; /* enum pg_states */ + /** @ref pg_states */ + uint32_t state; } __ABI_PACKED; struct cmd_pg_get_name_response { @@ -1291,8 +1339,7 @@ struct cmd_pg_get_max_id_response { } __ABI_PACKED; /** - * @ingroup Powergating - * @brief request with #MRQ_PG + * @brief Request with #MRQ_PG * * Used by the sender of an #MRQ_PG message to control power * partitions. The pg_request is split into several sub-commands. Some @@ -1308,7 +1355,6 @@ struct cmd_pg_get_max_id_response { * |CMD_PG_GET_MAX_ID | - | * */ - struct mrq_pg_request { uint32_t cmd; uint32_t id; @@ -1319,8 +1365,7 @@ struct mrq_pg_request { } __ABI_PACKED; /** - * @ingroup Powergating - * @brief response to MRQ_PG + * @brief Response to MRQ_PG * * Each sub-command supported by @ref mrq_pg_request may return * sub-command-specific data. Some do and some do not as indicated in @@ -1333,9 +1378,7 @@ struct mrq_pg_request { * |CMD_PG_GET_STATE | get_state | * |CMD_PG_GET_NAME | get_name | * |CMD_PG_GET_MAX_ID | get_max_id | - * */ - struct mrq_pg_response { union { struct cmd_pg_get_state_response get_state; @@ -1344,12 +1387,14 @@ struct mrq_pg_response { } __UNION_ANON; } __ABI_PACKED; +/** @} */ + /** * @ingroup MRQ_Codes * @def MRQ_THERMAL - * @brief interact with BPMP thermal framework + * @brief Interact with BPMP thermal framework * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: Any * * Request Payload: TODO @@ -1562,17 +1607,18 @@ union mrq_thermal_bpmp_to_host_response { * @brief Query CPU voltage hint data * * * Platforms: T186 + * @cond bpmp_t186 * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_cpu_vhint_request * * Response Payload: N/A * - * @addtogroup Vhint CPU Voltage hint + * @addtogroup Vhint * @{ */ /** - * @brief request with #MRQ_CPU_VHINT + * @brief Request with #MRQ_CPU_VHINT * * Used by #MRQ_CPU_VHINT call by CCPLEX to retrieve voltage hint data * from BPMP to memory space pointed by #addr. CCPLEX is responsible @@ -1581,16 +1627,16 @@ union mrq_thermal_bpmp_to_host_response { */ struct mrq_cpu_vhint_request { /** @brief IOVA address for the #cpu_vhint_data */ - uint32_t addr; /* struct cpu_vhint_data * */ + uint32_t addr; /** @brief ID of the cluster whose data is requested */ - uint32_t cluster_id; /* enum cluster_id */ + uint32_t cluster_id; } __ABI_PACKED; /** - * @brief description of the CPU v/f relation + * @brief Description of the CPU v/f relation * - * Used by #MRQ_CPU_VHINT call to carry data pointed by #addr of - * struct mrq_cpu_vhint_request + * Used by #MRQ_CPU_VHINT call to carry data pointed by + * #mrq_cpu_vhint_request::addr */ struct cpu_vhint_data { uint32_t ref_clk_hz; /**< reference frequency in Hz */ @@ -1612,7 +1658,7 @@ struct cpu_vhint_data { /** reserved for future use */ uint16_t reserved[328]; } __ABI_PACKED; - +/** @endcond */ /** @} */ /** @@ -1620,7 +1666,7 @@ struct cpu_vhint_data { * @def MRQ_ABI_RATCHET * @brief ABI ratchet value query * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_abi_ratchet_request @@ -1630,7 +1676,7 @@ struct cpu_vhint_data { */ /** - * @brief an ABI compatibility mechanism + * @brief An ABI compatibility mechanism * * BPMP_ABI_RATCHET_VALUE may increase for various reasons in a future * revision of this header file. @@ -1644,7 +1690,7 @@ struct cpu_vhint_data { #define BPMP_ABI_RATCHET_VALUE 3 /** - * @brief request with #MRQ_ABI_RATCHET. + * @brief Request with #MRQ_ABI_RATCHET. * * #ratchet should be #BPMP_ABI_RATCHET_VALUE from the ABI header * against which the requester was compiled. @@ -1657,12 +1703,12 @@ struct cpu_vhint_data { * Otherwise, err shall be 0. */ struct mrq_abi_ratchet_request { - /** @brief requester's ratchet value */ + /** @brief Requester's ratchet value */ uint16_t ratchet; }; /** - * @brief response to #MRQ_ABI_RATCHET + * @brief Response to #MRQ_ABI_RATCHET * * #ratchet shall be #BPMP_ABI_RATCHET_VALUE from the ABI header * against which BPMP firwmare was compiled. @@ -1685,9 +1731,9 @@ struct mrq_abi_ratchet_response { /** * @ingroup MRQ_Codes * @def MRQ_EMC_DVFS_LATENCY - * @brief query frequency dependent EMC DVFS latency + * @brief Query frequency dependent EMC DVFS latency * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: N/A @@ -1697,7 +1743,7 @@ struct mrq_abi_ratchet_response { */ /** - * @brief used by @ref mrq_emc_dvfs_latency_response + * @brief Used by @ref mrq_emc_dvfs_latency_response */ struct emc_dvfs_latency { /** @brief EMC frequency in kHz */ @@ -1708,10 +1754,10 @@ struct emc_dvfs_latency { #define EMC_DVFS_LATENCY_MAX_SIZE 14 /** - * @brief response to #MRQ_EMC_DVFS_LATENCY + * @brief Response to #MRQ_EMC_DVFS_LATENCY */ struct mrq_emc_dvfs_latency_response { - /** @brief the number valid entries in #pairs */ + /** @brief The number valid entries in #pairs */ uint32_t num_pairs; /** @brief EMC information */ struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE]; @@ -1719,10 +1765,98 @@ struct mrq_emc_dvfs_latency_response { /** @} */ +/** + * @ingroup MRQ_Codes + * @def MRQ_CPU_NDIV_LIMITS + * @brief CPU freq. limits in ndiv + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_cpu_ndiv_limits_request + * * Response Payload: @ref mrq_cpu_ndiv_limits_response + * @addtogroup CPU + * @{ + */ + +/** + * @brief Request for ndiv limits of a cluster + */ +struct mrq_cpu_ndiv_limits_request { + /** @brief Enum cluster_id */ + uint32_t cluster_id; +} __ABI_PACKED; + +/** + * @brief Response to #MRQ_CPU_NDIV_LIMITS + */ +struct mrq_cpu_ndiv_limits_response { + /** @brief Reference frequency in Hz */ + uint32_t ref_clk_hz; + /** @brief Post divider value */ + uint16_t pdiv; + /** @brief Input divider value */ + uint16_t mdiv; + /** @brief FMAX expressed with max NDIV value */ + uint16_t ndiv_max; + /** @brief Minimum allowed NDIV value */ + uint16_t ndiv_min; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_CPU_AUTO_CC3 + * @brief Query CPU cluster auto-CC3 configuration + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_cpu_auto_cc3_request + * * Response Payload: @ref mrq_cpu_auto_cc3_response + * @addtogroup CC3 + * + * Queries from BPMP auto-CC3 configuration (allowed/not allowed) for a + * specified cluster. CCPLEX s/w uses this information to override its own + * device tree auto-CC3 settings, so that BPMP device tree is a single source of + * auto-CC3 platform configuration. + * + * @{ + */ + +/** + * @brief Request for auto-CC3 configuration of a cluster + */ +struct mrq_cpu_auto_cc3_request { + /** @brief Enum cluster_id (logical cluster id, known to CCPLEX s/w) */ + uint32_t cluster_id; +} __ABI_PACKED; + +/** + * @brief Response to #MRQ_CPU_AUTO_CC3 + */ +struct mrq_cpu_auto_cc3_response { + /** + * @brief auto-CC3 configuration + * + * - bits[31..10] reserved. + * - bits[9..1] cc3 ndiv + * - bit [0] if "1" auto-CC3 is allowed, if "0" auto-CC3 is not allowed + */ + uint32_t auto_cc3_config; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + /** * @ingroup MRQ_Codes * @def MRQ_TRACE_ITER - * @brief manage the trace iterator + * @brief Manage the trace iterator * * * Platforms: All * * Initiators: CCPLEX @@ -1735,12 +1869,12 @@ struct mrq_emc_dvfs_latency_response { enum { /** @brief (re)start the tracing now. Ignore older events */ TRACE_ITER_INIT = 0, - /** @brief clobber all events in the trace buffer */ + /** @brief Clobber all events in the trace buffer */ TRACE_ITER_CLEAN = 1 }; /** - * @brief request with #MRQ_TRACE_ITER + * @brief Request with #MRQ_TRACE_ITER */ struct mrq_trace_iter_request { /** @brief TRACE_ITER_INIT or TRACE_ITER_CLEAN */ @@ -1900,7 +2034,7 @@ struct cmd_ringbuf_console_get_fifo_resp { */ struct mrq_ringbuf_console_host_to_bpmp_request { /** - * @brief type of request. Values listed in enum + * @brief Type of request. Values listed in enum * #mrq_ringbuf_console_host_to_bpmp_cmd. */ uint32_t type; @@ -1927,49 +2061,616 @@ union mrq_ringbuf_console_bpmp_to_host_response { } __ABI_PACKED; /** @} */ -/* - * 4. Enumerations +/** + * @ingroup MRQ_Codes + * @def MRQ_STRAP + * @brief Set a strap value controlled by BPMP + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_strap_request + * * Response Payload: N/A + * @addtogroup Strap + * + * A strap is an input that is sampled by a hardware unit during the + * unit's startup process. The sampled value of a strap affects the + * behavior of the unit until the unit is restarted. Many hardware + * units sample their straps at the instant that their resets are + * deasserted. + * + * BPMP owns registers which act as straps to various units. It + * exposes limited control of those straps via #MRQ_STRAP. + * + * @{ */ +enum mrq_strap_cmd { + /** @private */ + STRAP_RESERVED = 0, + /** @brief Set a strap value */ + STRAP_SET = 1 +}; -/* - * 4.1 CPU enumerations +/** + * @brief Request with #MRQ_STRAP + */ +struct mrq_strap_request { + /** @brief @ref mrq_strap_cmd */ + uint32_t cmd; + /** @brief Strap ID from @ref Strap_Ids */ + uint32_t id; + /** @brief Desired value for strap (if cmd is #STRAP_SET) */ + uint32_t value; +} __ABI_PACKED; + +/** + * @defgroup Strap_Ids Strap Identifiers + * @} + */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_UPHY + * @brief Perform a UPHY operation * - * See + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_uphy_request + * * Response Payload: @ref mrq_uphy_response * - * 4.2 CPU Cluster enumerations + * @addtogroup UPHY + * @{ + */ +enum { + CMD_UPHY_PCIE_LANE_MARGIN_CONTROL = 1, + CMD_UPHY_PCIE_LANE_MARGIN_STATUS = 2, + CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT = 3, + CMD_UPHY_PCIE_CONTROLLER_STATE = 4, + CMD_UPHY_MAX, +}; + +struct cmd_uphy_margin_control_request { + /** @brief Enable margin */ + int32_t en; + /** @brief Clear the number of error and sections */ + int32_t clr; + /** @brief Set x offset (1's complement) for left/right margin type (y should be 0) */ + uint32_t x; + /** @brief Set y offset (1's complement) for left/right margin type (x should be 0) */ + uint32_t y; + /** @brief Set number of bit blocks for each margin section */ + uint32_t nblks; +} __ABI_PACKED; + +struct cmd_uphy_margin_status_response { + /** @brief Number of errors observed */ + uint32_t status; +} __ABI_PACKED; + +struct cmd_uphy_ep_controller_pll_init_request { + /** @brief EP controller number, valid: 0, 4, 5 */ + uint8_t ep_controller; +} __ABI_PACKED; + +struct cmd_uphy_pcie_controller_state_request { + /** @brief PCIE controller number, valid: 0, 1, 2, 3, 4 */ + uint8_t pcie_controller; + uint8_t enable; +} __ABI_PACKED; + +/** + * @ingroup UPHY + * @brief Request with #MRQ_UPHY * - * See + * Used by the sender of an #MRQ_UPHY message to control UPHY Lane RX margining. + * The uphy_request is split into several sub-commands. Some sub-commands + * require no additional data. Others have a sub-command specific payload * - * 4.3 System low power state enumerations + * |sub-command |payload | + * |------------------------------------ |----------------------------------------| + * |CMD_UPHY_PCIE_LANE_MARGIN_CONTROL |uphy_set_margin_control | + * |CMD_UPHY_PCIE_LANE_MARGIN_STATUS | | + * |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT |cmd_uphy_ep_controller_pll_init_request | + * |CMD_UPHY_PCIE_CONTROLLER_STATE |cmd_uphy_pcie_controller_state_request | * - * See */ -/* - * 4.4 Clock enumerations +struct mrq_uphy_request { + /** @brief Lane number. */ + uint16_t lane; + /** @brief Sub-command id. */ + uint16_t cmd; + + union { + struct cmd_uphy_margin_control_request uphy_set_margin_control; + struct cmd_uphy_ep_controller_pll_init_request ep_ctrlr_pll_init; + struct cmd_uphy_pcie_controller_state_request controller_state; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup UPHY + * @brief Response to MRQ_UPHY + * + * Each sub-command supported by @ref mrq_uphy_request may return + * sub-command-specific data. Some do and some do not as indicated in + * the following table + * + * |sub-command |payload | + * |---------------------------- |------------------------| + * |CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | | + * |CMD_UPHY_PCIE_LANE_MARGIN_STATUS |uphy_get_margin_status | * - * For clock enumerations, see */ -/* - * 4.5 Reset enumerations +struct mrq_uphy_response { + union { + struct cmd_uphy_margin_status_response uphy_get_margin_status; + } __UNION_ANON; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_FMON + * @brief Perform a frequency monitor configuration operations + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_fmon_request + * * Response Payload: @ref mrq_fmon_response * - * For reset enumerations, see + * @addtogroup FMON + * @{ */ +enum { + /** + * @brief Clamp FMON configuration to specified rate. + * + * The monitored clock must be running for clamp to succeed. If + * clamped, FMON configuration is preserved when clock rate + * and/or state is changed. + */ + CMD_FMON_GEAR_CLAMP = 1, + /** + * @brief Release clamped FMON configuration. + * + * Allow FMON configuration to follow monitored clock rate + * and/or state changes. + */ + CMD_FMON_GEAR_FREE = 2, + /** + * @brief Return rate FMON is clamped at, or 0 if FMON is not + * clamped. + * + * Inherently racy, since clamp state can be changed + * concurrently. Useful for testing. + */ + CMD_FMON_GEAR_GET = 3, + CMD_FMON_NUM, +}; -/* - * 4.6 Thermal sensor enumerations +struct cmd_fmon_gear_clamp_request { + int32_t unused; + int64_t rate; +} __ABI_PACKED; + +/** @private */ +struct cmd_fmon_gear_clamp_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_fmon_gear_free_request { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_fmon_gear_free_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_fmon_gear_get_request { + EMPTY +} __ABI_PACKED; + +struct cmd_fmon_gear_get_response { + int64_t rate; +} __ABI_PACKED; + +/** + * @ingroup FMON + * @brief Request with #MRQ_FMON + * + * Used by the sender of an #MRQ_FMON message to configure clock + * frequency monitors. The FMON request is split into several + * sub-commands. Some sub-commands require no additional data. + * Others have a sub-command specific payload + * + * |sub-command |payload | + * |----------------------------|-----------------------| + * |CMD_FMON_GEAR_CLAMP |fmon_gear_clamp | + * |CMD_FMON_GEAR_FREE |- | + * |CMD_FMON_GEAR_GET |- | + * + */ + +struct mrq_fmon_request { + /** @brief Sub-command and clock id concatenated to 32-bit word. + * - bits[31..24] is the sub-cmd. + * - bits[23..0] is monitored clock id used to select target + * FMON + */ + uint32_t cmd_and_id; + + union { + struct cmd_fmon_gear_clamp_request fmon_gear_clamp; + /** @private */ + struct cmd_fmon_gear_free_request fmon_gear_free; + /** @private */ + struct cmd_fmon_gear_get_request fmon_gear_get; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup FMON + * @brief Response to MRQ_FMON + * + * Each sub-command supported by @ref mrq_fmon_request may + * return sub-command-specific data as indicated below. + * + * |sub-command |payload | + * |----------------------------|------------------------| + * |CMD_FMON_GEAR_CLAMP |- | + * |CMD_FMON_GEAR_FREE |- | + * |CMD_FMON_GEAR_GET |fmon_gear_get | + * + */ + +struct mrq_fmon_response { + union { + /** @private */ + struct cmd_fmon_gear_clamp_response fmon_gear_clamp; + /** @private */ + struct cmd_fmon_gear_free_response fmon_gear_free; + struct cmd_fmon_gear_get_response fmon_gear_get; + } __UNION_ANON; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_EC + * @brief Provide status information on faults reported by Error + * Collator (EC) to HSM. + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_ec_request + * * Response Payload: @ref mrq_ec_response + * + * @note This MRQ ABI is under construction, and subject to change + * + * @addtogroup EC + * @{ + */ +enum { + /** + * @brief Retrieve specified EC status. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_ENODEV if target EC is not owned by BPMP @n + * -#BPMP_EACCES if target EC power domain is turned off + */ + CMD_EC_STATUS_GET = 1, + CMD_EC_NUM, +}; + +/** @brief BPMP ECs error types */ +enum bpmp_ec_err_type { + /** @brief Parity error on internal data path + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_PARITY_INTERNAL = 1, + + /** @brief ECC SEC error on internal data path + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_ECC_SEC_INTERNAL = 2, + + /** @brief ECC DED error on internal data path + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_ECC_DED_INTERNAL = 3, + + /** @brief Comparator error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_COMPARATOR = 4, + + /** @brief Register parity error + * + * Error descriptor @ref ec_err_reg_parity_desc. + */ + EC_ERR_TYPE_REGISTER_PARITY = 5, + + /** @brief Parity error from on-chip SRAM/FIFO + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_PARITY_SRAM = 6, + + /** @brief Clock Monitor error + * + * Error descriptor @ref ec_err_fmon_desc. + */ + EC_ERR_TYPE_CLOCK_MONITOR = 9, + + /** @brief Voltage Monitor error + * + * Error descriptor @ref ec_err_vmon_desc. + */ + EC_ERR_TYPE_VOLTAGE_MONITOR = 10, + + /** @brief SW Correctable error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_SW_CORRECTABLE = 16, + + /** @brief SW Uncorrectable error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_SW_UNCORRECTABLE = 17, + + /** @brief Other HW Correctable error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_OTHER_HW_CORRECTABLE = 32, + + /** @brief Other HW Uncorrectable error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_OTHER_HW_UNCORRECTABLE = 33, +}; + +/** @brief Group of registers with parity error. */ +enum ec_registers_group { + /** @brief Functional registers group */ + EC_ERR_GROUP_FUNC_REG = 0, + /** @brief SCR registers group */ + EC_ERR_GROUP_SCR_REG = 1, +}; + +/** + * @defgroup bpmp_ec_status_flags EC Status Flags + * @addtogroup bpmp_ec_status_flags + * @{ + */ +/** @brief No EC error found flag */ +#define EC_STATUS_FLAG_NO_ERROR 0x0001 +/** @brief Last EC error found flag */ +#define EC_STATUS_FLAG_LAST_ERROR 0x0002 +/** @brief EC latent error flag */ +#define EC_STATUS_FLAG_LATENT_ERROR 0x0004 +/** @} */ + +/** + * @defgroup bpmp_ec_desc_flags EC Descriptor Flags + * @addtogroup bpmp_ec_desc_flags + * @{ + */ +/** @brief EC descriptor error resolved flag */ +#define EC_DESC_FLAG_RESOLVED 0x0001 +/** @brief EC descriptor failed to retrieve id flag */ +#define EC_DESC_FLAG_NO_ID 0x0002 +/** @} */ + +/** + * |error type | fmon_clk_id values | + * |---------------------------------|---------------------------| + * |@ref EC_ERR_TYPE_CLOCK_MONITOR |@ref bpmp_clock_ids | + */ +struct ec_err_fmon_desc { + /** @brief Bitmask of @ref bpmp_ec_desc_flags */ + uint16_t desc_flags; + /** @brief FMON monitored clock id */ + uint16_t fmon_clk_id; + /** @brief Bitmask of @ref bpmp_fmon_faults_flags */ + uint32_t fmon_faults; + /** @brief FMON faults access error */ + int32_t fmon_access_error; +} __ABI_PACKED; + +/** + * |error type | vmon_adc_id values | + * |---------------------------------|---------------------------| + * |@ref EC_ERR_TYPE_VOLTAGE_MONITOR |@ref bpmp_adc_ids | + */ +struct ec_err_vmon_desc { + /** @brief Bitmask of @ref bpmp_ec_desc_flags */ + uint16_t desc_flags; + /** @brief VMON rail adc id */ + uint16_t vmon_adc_id; + /** @brief Bitmask of @ref bpmp_vmon_faults_flags */ + uint32_t vmon_faults; + /** @brief VMON faults access error */ + int32_t vmon_access_error; +} __ABI_PACKED; + +/** + * |error type | reg_id values | + * |---------------------------------|---------------------------| + * |@ref EC_ERR_TYPE_REGISTER_PARITY |@ref bpmp_ec_registers_ids | + */ +struct ec_err_reg_parity_desc { + /** @brief Bitmask of @ref bpmp_ec_desc_flags */ + uint16_t desc_flags; + /** @brief Register id */ + uint16_t reg_id; + /** @brief Register group @ref ec_registers_group */ + uint16_t reg_group; +} __ABI_PACKED; + +/** + * |error type | err_source_id values | + * |----------------------------------------|---------------------------| + * |@ref EC_ERR_TYPE_PARITY_INTERNAL |@ref bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_ECC_SEC_INTERNAL |@ref bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_ECC_DED_INTERNAL |@ref bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_COMPARATOR |@ref bpmp_ec_comparator_ids| + * |@ref EC_ERR_TYPE_PARITY_SRAM |@ref bpmp_clock_ids | + * |@ref EC_ERR_TYPE_SW_CORRECTABLE |@ref bpmp_ec_misc_ids | + * |@ref EC_ERR_TYPE_SW_UNCORRECTABLE |@ref bpmp_ec_misc_ids | + * |@ref EC_ERR_TYPE_OTHER_HW_CORRECTABLE |@ref bpmp_ec_misc_ids | + * |@ref EC_ERR_TYPE_OTHER_HW_UNCORRECTABLE |@ref bpmp_ec_misc_ids | + */ +struct ec_err_simple_desc { + /** @brief Bitmask of @ref bpmp_ec_desc_flags */ + uint16_t desc_flags; + /** @brief Error source id. Id space depends on error type. */ + uint16_t err_source_id; +} __ABI_PACKED; + +/** @brief Union of EC error descriptors */ +union ec_err_desc { + struct ec_err_fmon_desc fmon_desc; + struct ec_err_vmon_desc vmon_desc; + struct ec_err_reg_parity_desc reg_parity_desc; + struct ec_err_simple_desc simple_desc; +} __ABI_PACKED; + +struct cmd_ec_status_get_request { + /** @brief HSM error line number that identifies target EC. */ + uint32_t ec_hsm_id; +} __ABI_PACKED; + +/** EC status maximum number of descriptors */ +#define EC_ERR_STATUS_DESC_MAX_NUM 4 + +struct cmd_ec_status_get_response { + /** @brief Target EC id (the same id received with request). */ + uint32_t ec_hsm_id; + /** + * @brief Bitmask of @ref bpmp_ec_status_flags + * + * If NO_ERROR flag is set, error_ fields should be ignored + */ + uint32_t ec_status_flags; + /** @brief Found EC error index. */ + uint32_t error_idx; + /** @brief Found EC error type @ref bpmp_ec_err_type. */ + uint32_t error_type; + /** @brief Number of returned EC error descriptors */ + uint32_t error_desc_num; + /** @brief EC error descriptors */ + union ec_err_desc error_descs[EC_ERR_STATUS_DESC_MAX_NUM]; +} __ABI_PACKED; + +/** + * @ingroup EC + * @brief Request with #MRQ_EC + * + * Used by the sender of an #MRQ_EC message to access ECs owned + * by BPMP. + * + * |sub-command |payload | + * |----------------------------|-----------------------| + * |@ref CMD_EC_STATUS_GET |ec_status_get | * - * For thermal sensor enumerations, see */ +struct mrq_ec_request { + /** @brief Sub-command id. */ + uint32_t cmd_id; + + union { + struct cmd_ec_status_get_request ec_status_get; + } __UNION_ANON; +} __ABI_PACKED; + /** - * @defgroup Error_Codes + * @ingroup EC + * @brief Response to MRQ_EC + * + * Each sub-command supported by @ref mrq_ec_request may return + * sub-command-specific data as indicated below. + * + * |sub-command |payload | + * |----------------------------|------------------------| + * |@ref CMD_EC_STATUS_GET |ec_status_get | + * + */ + +struct mrq_ec_response { + union { + struct cmd_ec_status_get_response ec_status_get; + } __UNION_ANON; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_FBVOLT_STATUS + * @brief Provides status information about voltage state for fuse burning + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Target: BPMP + * * Request Payload: None + * * Response Payload: @ref mrq_fbvolt_status_response + * @{ + */ + +/** + * @ingroup Fbvolt_status + * @brief Response to #MRQ_FBVOLT_STATUS + * + * Value of #ready reflects if core voltages are in a suitable state for buring + * fuses. A value of 0x1 indicates that core voltages are ready for burning + * fuses. A value of 0x0 indicates that core voltages are not ready. + */ +struct mrq_fbvolt_status_response { + /** @brief Bit [0:0] - ready status, bits [31:1] - reserved */ + uint32_t ready; + /** @brief Reserved */ + uint32_t unused; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @addtogroup Error_Codes * Negative values for mrq_response::err generally indicate some * error. The ABI defines the following error codes. Negating these * defines is an exercise left to the user. * @{ */ + /** @brief No such file or directory */ #define BPMP_ENOENT 2 /** @brief No MRQ handler */ @@ -1994,6 +2695,11 @@ union mrq_ringbuf_console_bpmp_to_host_response { #define BPMP_ETIMEDOUT 23 /** @brief Out of range */ #define BPMP_ERANGE 34 +/** @brief Function not implemented */ +#define BPMP_ENOSYS 38 +/** @brief Invalid slot */ +#define BPMP_EBADSLT 57 + /** @} */ -/** @} */ + #endif -- cgit v1.2.3 From 1866d58be7ec02b656ef913a46eb1f0c5ff2b25f Mon Sep 17 00:00:00 2001 From: Bo Yan Date: Tue, 13 Nov 2018 09:51:05 -0800 Subject: soc/tegra: fuse: Remove duplicated function declaration The function tegra_read_chipid() is declared twice in fuse.h. Remove the redundant declaration. Signed-off-by: Bo Yan Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- include/soc/tegra/fuse.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 9b6ea0c72117..8fb2f8a87339 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -60,7 +60,6 @@ struct tegra_sku_info { u32 tegra_read_straps(void); u32 tegra_read_ram_code(void); -u32 tegra_read_chipid(void); int tegra_fuse_readl(unsigned long offset, u32 *value); extern struct tegra_sku_info tegra_sku_info; -- cgit v1.2.3 From d4ea45e8a6031504b87cef76944c8730c67fec1f Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Thu, 1 Nov 2018 15:19:53 +0000 Subject: dt-bindings: imx: add scu resource id headfile SCU firmware uses resource id to provide services. Every device on a SCU based system has a resource id. Exported it in device tree to allow service bindings to use it. e.g. power domain. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Mark Rutland Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Reviewed-by: Ulf Hansson Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- include/dt-bindings/firmware/imx/rsrc.h | 559 ++++++++++++++++++++++++++++++++ 1 file changed, 559 insertions(+) create mode 100644 include/dt-bindings/firmware/imx/rsrc.h (limited to 'include') diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h new file mode 100644 index 000000000000..4481f2d60d65 --- /dev/null +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -0,0 +1,559 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#ifndef __DT_BINDINGS_RSCRC_IMX_H +#define __DT_BINDINGS_RSCRC_IMX_H + +/* + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ + +#define IMX_SC_R_A53 0 +#define IMX_SC_R_A53_0 1 +#define IMX_SC_R_A53_1 2 +#define IMX_SC_R_A53_2 3 +#define IMX_SC_R_A53_3 4 +#define IMX_SC_R_A72 5 +#define IMX_SC_R_A72_0 6 +#define IMX_SC_R_A72_1 7 +#define IMX_SC_R_A72_2 8 +#define IMX_SC_R_A72_3 9 +#define IMX_SC_R_CCI 10 +#define IMX_SC_R_DB 11 +#define IMX_SC_R_DRC_0 12 +#define IMX_SC_R_DRC_1 13 +#define IMX_SC_R_GIC_SMMU 14 +#define IMX_SC_R_IRQSTR_M4_0 15 +#define IMX_SC_R_IRQSTR_M4_1 16 +#define IMX_SC_R_SMMU 17 +#define IMX_SC_R_GIC 18 +#define IMX_SC_R_DC_0_BLIT0 19 +#define IMX_SC_R_DC_0_BLIT1 20 +#define IMX_SC_R_DC_0_BLIT2 21 +#define IMX_SC_R_DC_0_BLIT_OUT 22 +#define IMX_SC_R_DC_0_CAPTURE0 23 +#define IMX_SC_R_DC_0_CAPTURE1 24 +#define IMX_SC_R_DC_0_WARP 25 +#define IMX_SC_R_DC_0_INTEGRAL0 26 +#define IMX_SC_R_DC_0_INTEGRAL1 27 +#define IMX_SC_R_DC_0_VIDEO0 28 +#define IMX_SC_R_DC_0_VIDEO1 29 +#define IMX_SC_R_DC_0_FRAC0 30 +#define IMX_SC_R_DC_0_FRAC1 31 +#define IMX_SC_R_DC_0 32 +#define IMX_SC_R_GPU_2_PID0 33 +#define IMX_SC_R_DC_0_PLL_0 34 +#define IMX_SC_R_DC_0_PLL_1 35 +#define IMX_SC_R_DC_1_BLIT0 36 +#define IMX_SC_R_DC_1_BLIT1 37 +#define IMX_SC_R_DC_1_BLIT2 38 +#define IMX_SC_R_DC_1_BLIT_OUT 39 +#define IMX_SC_R_DC_1_CAPTURE0 40 +#define IMX_SC_R_DC_1_CAPTURE1 41 +#define IMX_SC_R_DC_1_WARP 42 +#define IMX_SC_R_DC_1_INTEGRAL0 43 +#define IMX_SC_R_DC_1_INTEGRAL1 44 +#define IMX_SC_R_DC_1_VIDEO0 45 +#define IMX_SC_R_DC_1_VIDEO1 46 +#define IMX_SC_R_DC_1_FRAC0 47 +#define IMX_SC_R_DC_1_FRAC1 48 +#define IMX_SC_R_DC_1 49 +#define IMX_SC_R_GPU_3_PID0 50 +#define IMX_SC_R_DC_1_PLL_0 51 +#define IMX_SC_R_DC_1_PLL_1 52 +#define IMX_SC_R_SPI_0 53 +#define IMX_SC_R_SPI_1 54 +#define IMX_SC_R_SPI_2 55 +#define IMX_SC_R_SPI_3 56 +#define IMX_SC_R_UART_0 57 +#define IMX_SC_R_UART_1 58 +#define IMX_SC_R_UART_2 59 +#define IMX_SC_R_UART_3 60 +#define IMX_SC_R_UART_4 61 +#define IMX_SC_R_EMVSIM_0 62 +#define IMX_SC_R_EMVSIM_1 63 +#define IMX_SC_R_DMA_0_CH0 64 +#define IMX_SC_R_DMA_0_CH1 65 +#define IMX_SC_R_DMA_0_CH2 66 +#define IMX_SC_R_DMA_0_CH3 67 +#define IMX_SC_R_DMA_0_CH4 68 +#define IMX_SC_R_DMA_0_CH5 69 +#define IMX_SC_R_DMA_0_CH6 70 +#define IMX_SC_R_DMA_0_CH7 71 +#define IMX_SC_R_DMA_0_CH8 72 +#define IMX_SC_R_DMA_0_CH9 73 +#define IMX_SC_R_DMA_0_CH10 74 +#define IMX_SC_R_DMA_0_CH11 75 +#define IMX_SC_R_DMA_0_CH12 76 +#define IMX_SC_R_DMA_0_CH13 77 +#define IMX_SC_R_DMA_0_CH14 78 +#define IMX_SC_R_DMA_0_CH15 79 +#define IMX_SC_R_DMA_0_CH16 80 +#define IMX_SC_R_DMA_0_CH17 81 +#define IMX_SC_R_DMA_0_CH18 82 +#define IMX_SC_R_DMA_0_CH19 83 +#define IMX_SC_R_DMA_0_CH20 84 +#define IMX_SC_R_DMA_0_CH21 85 +#define IMX_SC_R_DMA_0_CH22 86 +#define IMX_SC_R_DMA_0_CH23 87 +#define IMX_SC_R_DMA_0_CH24 88 +#define IMX_SC_R_DMA_0_CH25 89 +#define IMX_SC_R_DMA_0_CH26 90 +#define IMX_SC_R_DMA_0_CH27 91 +#define IMX_SC_R_DMA_0_CH28 92 +#define IMX_SC_R_DMA_0_CH29 93 +#define IMX_SC_R_DMA_0_CH30 94 +#define IMX_SC_R_DMA_0_CH31 95 +#define IMX_SC_R_I2C_0 96 +#define IMX_SC_R_I2C_1 97 +#define IMX_SC_R_I2C_2 98 +#define IMX_SC_R_I2C_3 99 +#define IMX_SC_R_I2C_4 100 +#define IMX_SC_R_ADC_0 101 +#define IMX_SC_R_ADC_1 102 +#define IMX_SC_R_FTM_0 103 +#define IMX_SC_R_FTM_1 104 +#define IMX_SC_R_CAN_0 105 +#define IMX_SC_R_CAN_1 106 +#define IMX_SC_R_CAN_2 107 +#define IMX_SC_R_DMA_1_CH0 108 +#define IMX_SC_R_DMA_1_CH1 109 +#define IMX_SC_R_DMA_1_CH2 110 +#define IMX_SC_R_DMA_1_CH3 111 +#define IMX_SC_R_DMA_1_CH4 112 +#define IMX_SC_R_DMA_1_CH5 113 +#define IMX_SC_R_DMA_1_CH6 114 +#define IMX_SC_R_DMA_1_CH7 115 +#define IMX_SC_R_DMA_1_CH8 116 +#define IMX_SC_R_DMA_1_CH9 117 +#define IMX_SC_R_DMA_1_CH10 118 +#define IMX_SC_R_DMA_1_CH11 119 +#define IMX_SC_R_DMA_1_CH12 120 +#define IMX_SC_R_DMA_1_CH13 121 +#define IMX_SC_R_DMA_1_CH14 122 +#define IMX_SC_R_DMA_1_CH15 123 +#define IMX_SC_R_DMA_1_CH16 124 +#define IMX_SC_R_DMA_1_CH17 125 +#define IMX_SC_R_DMA_1_CH18 126 +#define IMX_SC_R_DMA_1_CH19 127 +#define IMX_SC_R_DMA_1_CH20 128 +#define IMX_SC_R_DMA_1_CH21 129 +#define IMX_SC_R_DMA_1_CH22 130 +#define IMX_SC_R_DMA_1_CH23 131 +#define IMX_SC_R_DMA_1_CH24 132 +#define IMX_SC_R_DMA_1_CH25 133 +#define IMX_SC_R_DMA_1_CH26 134 +#define IMX_SC_R_DMA_1_CH27 135 +#define IMX_SC_R_DMA_1_CH28 136 +#define IMX_SC_R_DMA_1_CH29 137 +#define IMX_SC_R_DMA_1_CH30 138 +#define IMX_SC_R_DMA_1_CH31 139 +#define IMX_SC_R_UNUSED1 140 +#define IMX_SC_R_UNUSED2 141 +#define IMX_SC_R_UNUSED3 142 +#define IMX_SC_R_UNUSED4 143 +#define IMX_SC_R_GPU_0_PID0 144 +#define IMX_SC_R_GPU_0_PID1 145 +#define IMX_SC_R_GPU_0_PID2 146 +#define IMX_SC_R_GPU_0_PID3 147 +#define IMX_SC_R_GPU_1_PID0 148 +#define IMX_SC_R_GPU_1_PID1 149 +#define IMX_SC_R_GPU_1_PID2 150 +#define IMX_SC_R_GPU_1_PID3 151 +#define IMX_SC_R_PCIE_A 152 +#define IMX_SC_R_SERDES_0 153 +#define IMX_SC_R_MATCH_0 154 +#define IMX_SC_R_MATCH_1 155 +#define IMX_SC_R_MATCH_2 156 +#define IMX_SC_R_MATCH_3 157 +#define IMX_SC_R_MATCH_4 158 +#define IMX_SC_R_MATCH_5 159 +#define IMX_SC_R_MATCH_6 160 +#define IMX_SC_R_MATCH_7 161 +#define IMX_SC_R_MATCH_8 162 +#define IMX_SC_R_MATCH_9 163 +#define IMX_SC_R_MATCH_10 164 +#define IMX_SC_R_MATCH_11 165 +#define IMX_SC_R_MATCH_12 166 +#define IMX_SC_R_MATCH_13 167 +#define IMX_SC_R_MATCH_14 168 +#define IMX_SC_R_PCIE_B 169 +#define IMX_SC_R_SATA_0 170 +#define IMX_SC_R_SERDES_1 171 +#define IMX_SC_R_HSIO_GPIO 172 +#define IMX_SC_R_MATCH_15 173 +#define IMX_SC_R_MATCH_16 174 +#define IMX_SC_R_MATCH_17 175 +#define IMX_SC_R_MATCH_18 176 +#define IMX_SC_R_MATCH_19 177 +#define IMX_SC_R_MATCH_20 178 +#define IMX_SC_R_MATCH_21 179 +#define IMX_SC_R_MATCH_22 180 +#define IMX_SC_R_MATCH_23 181 +#define IMX_SC_R_MATCH_24 182 +#define IMX_SC_R_MATCH_25 183 +#define IMX_SC_R_MATCH_26 184 +#define IMX_SC_R_MATCH_27 185 +#define IMX_SC_R_MATCH_28 186 +#define IMX_SC_R_LCD_0 187 +#define IMX_SC_R_LCD_0_PWM_0 188 +#define IMX_SC_R_LCD_0_I2C_0 189 +#define IMX_SC_R_LCD_0_I2C_1 190 +#define IMX_SC_R_PWM_0 191 +#define IMX_SC_R_PWM_1 192 +#define IMX_SC_R_PWM_2 193 +#define IMX_SC_R_PWM_3 194 +#define IMX_SC_R_PWM_4 195 +#define IMX_SC_R_PWM_5 196 +#define IMX_SC_R_PWM_6 197 +#define IMX_SC_R_PWM_7 198 +#define IMX_SC_R_GPIO_0 199 +#define IMX_SC_R_GPIO_1 200 +#define IMX_SC_R_GPIO_2 201 +#define IMX_SC_R_GPIO_3 202 +#define IMX_SC_R_GPIO_4 203 +#define IMX_SC_R_GPIO_5 204 +#define IMX_SC_R_GPIO_6 205 +#define IMX_SC_R_GPIO_7 206 +#define IMX_SC_R_GPT_0 207 +#define IMX_SC_R_GPT_1 208 +#define IMX_SC_R_GPT_2 209 +#define IMX_SC_R_GPT_3 210 +#define IMX_SC_R_GPT_4 211 +#define IMX_SC_R_KPP 212 +#define IMX_SC_R_MU_0A 213 +#define IMX_SC_R_MU_1A 214 +#define IMX_SC_R_MU_2A 215 +#define IMX_SC_R_MU_3A 216 +#define IMX_SC_R_MU_4A 217 +#define IMX_SC_R_MU_5A 218 +#define IMX_SC_R_MU_6A 219 +#define IMX_SC_R_MU_7A 220 +#define IMX_SC_R_MU_8A 221 +#define IMX_SC_R_MU_9A 222 +#define IMX_SC_R_MU_10A 223 +#define IMX_SC_R_MU_11A 224 +#define IMX_SC_R_MU_12A 225 +#define IMX_SC_R_MU_13A 226 +#define IMX_SC_R_MU_5B 227 +#define IMX_SC_R_MU_6B 228 +#define IMX_SC_R_MU_7B 229 +#define IMX_SC_R_MU_8B 230 +#define IMX_SC_R_MU_9B 231 +#define IMX_SC_R_MU_10B 232 +#define IMX_SC_R_MU_11B 233 +#define IMX_SC_R_MU_12B 234 +#define IMX_SC_R_MU_13B 235 +#define IMX_SC_R_ROM_0 236 +#define IMX_SC_R_FSPI_0 237 +#define IMX_SC_R_FSPI_1 238 +#define IMX_SC_R_IEE 239 +#define IMX_SC_R_IEE_R0 240 +#define IMX_SC_R_IEE_R1 241 +#define IMX_SC_R_IEE_R2 242 +#define IMX_SC_R_IEE_R3 243 +#define IMX_SC_R_IEE_R4 244 +#define IMX_SC_R_IEE_R5 245 +#define IMX_SC_R_IEE_R6 246 +#define IMX_SC_R_IEE_R7 247 +#define IMX_SC_R_SDHC_0 248 +#define IMX_SC_R_SDHC_1 249 +#define IMX_SC_R_SDHC_2 250 +#define IMX_SC_R_ENET_0 251 +#define IMX_SC_R_ENET_1 252 +#define IMX_SC_R_MLB_0 253 +#define IMX_SC_R_DMA_2_CH0 254 +#define IMX_SC_R_DMA_2_CH1 255 +#define IMX_SC_R_DMA_2_CH2 256 +#define IMX_SC_R_DMA_2_CH3 257 +#define IMX_SC_R_DMA_2_CH4 258 +#define IMX_SC_R_USB_0 259 +#define IMX_SC_R_USB_1 260 +#define IMX_SC_R_USB_0_PHY 261 +#define IMX_SC_R_USB_2 262 +#define IMX_SC_R_USB_2_PHY 263 +#define IMX_SC_R_DTCP 264 +#define IMX_SC_R_NAND 265 +#define IMX_SC_R_LVDS_0 266 +#define IMX_SC_R_LVDS_0_PWM_0 267 +#define IMX_SC_R_LVDS_0_I2C_0 268 +#define IMX_SC_R_LVDS_0_I2C_1 269 +#define IMX_SC_R_LVDS_1 270 +#define IMX_SC_R_LVDS_1_PWM_0 271 +#define IMX_SC_R_LVDS_1_I2C_0 272 +#define IMX_SC_R_LVDS_1_I2C_1 273 +#define IMX_SC_R_LVDS_2 274 +#define IMX_SC_R_LVDS_2_PWM_0 275 +#define IMX_SC_R_LVDS_2_I2C_0 276 +#define IMX_SC_R_LVDS_2_I2C_1 277 +#define IMX_SC_R_M4_0_PID0 278 +#define IMX_SC_R_M4_0_PID1 279 +#define IMX_SC_R_M4_0_PID2 280 +#define IMX_SC_R_M4_0_PID3 281 +#define IMX_SC_R_M4_0_PID4 282 +#define IMX_SC_R_M4_0_RGPIO 283 +#define IMX_SC_R_M4_0_SEMA42 284 +#define IMX_SC_R_M4_0_TPM 285 +#define IMX_SC_R_M4_0_PIT 286 +#define IMX_SC_R_M4_0_UART 287 +#define IMX_SC_R_M4_0_I2C 288 +#define IMX_SC_R_M4_0_INTMUX 289 +#define IMX_SC_R_M4_0_SIM 290 +#define IMX_SC_R_M4_0_WDOG 291 +#define IMX_SC_R_M4_0_MU_0B 292 +#define IMX_SC_R_M4_0_MU_0A0 293 +#define IMX_SC_R_M4_0_MU_0A1 294 +#define IMX_SC_R_M4_0_MU_0A2 295 +#define IMX_SC_R_M4_0_MU_0A3 296 +#define IMX_SC_R_M4_0_MU_1A 297 +#define IMX_SC_R_M4_1_PID0 298 +#define IMX_SC_R_M4_1_PID1 299 +#define IMX_SC_R_M4_1_PID2 300 +#define IMX_SC_R_M4_1_PID3 301 +#define IMX_SC_R_M4_1_PID4 302 +#define IMX_SC_R_M4_1_RGPIO 303 +#define IMX_SC_R_M4_1_SEMA42 304 +#define IMX_SC_R_M4_1_TPM 305 +#define IMX_SC_R_M4_1_PIT 306 +#define IMX_SC_R_M4_1_UART 307 +#define IMX_SC_R_M4_1_I2C 308 +#define IMX_SC_R_M4_1_INTMUX 309 +#define IMX_SC_R_M4_1_SIM 310 +#define IMX_SC_R_M4_1_WDOG 311 +#define IMX_SC_R_M4_1_MU_0B 312 +#define IMX_SC_R_M4_1_MU_0A0 313 +#define IMX_SC_R_M4_1_MU_0A1 314 +#define IMX_SC_R_M4_1_MU_0A2 315 +#define IMX_SC_R_M4_1_MU_0A3 316 +#define IMX_SC_R_M4_1_MU_1A 317 +#define IMX_SC_R_SAI_0 318 +#define IMX_SC_R_SAI_1 319 +#define IMX_SC_R_SAI_2 320 +#define IMX_SC_R_IRQSTR_SCU2 321 +#define IMX_SC_R_IRQSTR_DSP 322 +#define IMX_SC_R_ELCDIF_PLL 323 +#define IMX_SC_R_UNUSED6 324 +#define IMX_SC_R_AUDIO_PLL_0 325 +#define IMX_SC_R_PI_0 326 +#define IMX_SC_R_PI_0_PWM_0 327 +#define IMX_SC_R_PI_0_PWM_1 328 +#define IMX_SC_R_PI_0_I2C_0 329 +#define IMX_SC_R_PI_0_PLL 330 +#define IMX_SC_R_PI_1 331 +#define IMX_SC_R_PI_1_PWM_0 332 +#define IMX_SC_R_PI_1_PWM_1 333 +#define IMX_SC_R_PI_1_I2C_0 334 +#define IMX_SC_R_PI_1_PLL 335 +#define IMX_SC_R_SC_PID0 336 +#define IMX_SC_R_SC_PID1 337 +#define IMX_SC_R_SC_PID2 338 +#define IMX_SC_R_SC_PID3 339 +#define IMX_SC_R_SC_PID4 340 +#define IMX_SC_R_SC_SEMA42 341 +#define IMX_SC_R_SC_TPM 342 +#define IMX_SC_R_SC_PIT 343 +#define IMX_SC_R_SC_UART 344 +#define IMX_SC_R_SC_I2C 345 +#define IMX_SC_R_SC_MU_0B 346 +#define IMX_SC_R_SC_MU_0A0 347 +#define IMX_SC_R_SC_MU_0A1 348 +#define IMX_SC_R_SC_MU_0A2 349 +#define IMX_SC_R_SC_MU_0A3 350 +#define IMX_SC_R_SC_MU_1A 351 +#define IMX_SC_R_SYSCNT_RD 352 +#define IMX_SC_R_SYSCNT_CMP 353 +#define IMX_SC_R_DEBUG 354 +#define IMX_SC_R_SYSTEM 355 +#define IMX_SC_R_SNVS 356 +#define IMX_SC_R_OTP 357 +#define IMX_SC_R_VPU_PID0 358 +#define IMX_SC_R_VPU_PID1 359 +#define IMX_SC_R_VPU_PID2 360 +#define IMX_SC_R_VPU_PID3 361 +#define IMX_SC_R_VPU_PID4 362 +#define IMX_SC_R_VPU_PID5 363 +#define IMX_SC_R_VPU_PID6 364 +#define IMX_SC_R_VPU_PID7 365 +#define IMX_SC_R_VPU_UART 366 +#define IMX_SC_R_VPUCORE 367 +#define IMX_SC_R_VPUCORE_0 368 +#define IMX_SC_R_VPUCORE_1 369 +#define IMX_SC_R_VPUCORE_2 370 +#define IMX_SC_R_VPUCORE_3 371 +#define IMX_SC_R_DMA_4_CH0 372 +#define IMX_SC_R_DMA_4_CH1 373 +#define IMX_SC_R_DMA_4_CH2 374 +#define IMX_SC_R_DMA_4_CH3 375 +#define IMX_SC_R_DMA_4_CH4 376 +#define IMX_SC_R_ISI_CH0 377 +#define IMX_SC_R_ISI_CH1 378 +#define IMX_SC_R_ISI_CH2 379 +#define IMX_SC_R_ISI_CH3 380 +#define IMX_SC_R_ISI_CH4 381 +#define IMX_SC_R_ISI_CH5 382 +#define IMX_SC_R_ISI_CH6 383 +#define IMX_SC_R_ISI_CH7 384 +#define IMX_SC_R_MJPEG_DEC_S0 385 +#define IMX_SC_R_MJPEG_DEC_S1 386 +#define IMX_SC_R_MJPEG_DEC_S2 387 +#define IMX_SC_R_MJPEG_DEC_S3 388 +#define IMX_SC_R_MJPEG_ENC_S0 389 +#define IMX_SC_R_MJPEG_ENC_S1 390 +#define IMX_SC_R_MJPEG_ENC_S2 391 +#define IMX_SC_R_MJPEG_ENC_S3 392 +#define IMX_SC_R_MIPI_0 393 +#define IMX_SC_R_MIPI_0_PWM_0 394 +#define IMX_SC_R_MIPI_0_I2C_0 395 +#define IMX_SC_R_MIPI_0_I2C_1 396 +#define IMX_SC_R_MIPI_1 397 +#define IMX_SC_R_MIPI_1_PWM_0 398 +#define IMX_SC_R_MIPI_1_I2C_0 399 +#define IMX_SC_R_MIPI_1_I2C_1 400 +#define IMX_SC_R_CSI_0 401 +#define IMX_SC_R_CSI_0_PWM_0 402 +#define IMX_SC_R_CSI_0_I2C_0 403 +#define IMX_SC_R_CSI_1 404 +#define IMX_SC_R_CSI_1_PWM_0 405 +#define IMX_SC_R_CSI_1_I2C_0 406 +#define IMX_SC_R_HDMI 407 +#define IMX_SC_R_HDMI_I2S 408 +#define IMX_SC_R_HDMI_I2C_0 409 +#define IMX_SC_R_HDMI_PLL_0 410 +#define IMX_SC_R_HDMI_RX 411 +#define IMX_SC_R_HDMI_RX_BYPASS 412 +#define IMX_SC_R_HDMI_RX_I2C_0 413 +#define IMX_SC_R_ASRC_0 414 +#define IMX_SC_R_ESAI_0 415 +#define IMX_SC_R_SPDIF_0 416 +#define IMX_SC_R_SPDIF_1 417 +#define IMX_SC_R_SAI_3 418 +#define IMX_SC_R_SAI_4 419 +#define IMX_SC_R_SAI_5 420 +#define IMX_SC_R_GPT_5 421 +#define IMX_SC_R_GPT_6 422 +#define IMX_SC_R_GPT_7 423 +#define IMX_SC_R_GPT_8 424 +#define IMX_SC_R_GPT_9 425 +#define IMX_SC_R_GPT_10 426 +#define IMX_SC_R_DMA_2_CH5 427 +#define IMX_SC_R_DMA_2_CH6 428 +#define IMX_SC_R_DMA_2_CH7 429 +#define IMX_SC_R_DMA_2_CH8 430 +#define IMX_SC_R_DMA_2_CH9 431 +#define IMX_SC_R_DMA_2_CH10 432 +#define IMX_SC_R_DMA_2_CH11 433 +#define IMX_SC_R_DMA_2_CH12 434 +#define IMX_SC_R_DMA_2_CH13 435 +#define IMX_SC_R_DMA_2_CH14 436 +#define IMX_SC_R_DMA_2_CH15 437 +#define IMX_SC_R_DMA_2_CH16 438 +#define IMX_SC_R_DMA_2_CH17 439 +#define IMX_SC_R_DMA_2_CH18 440 +#define IMX_SC_R_DMA_2_CH19 441 +#define IMX_SC_R_DMA_2_CH20 442 +#define IMX_SC_R_DMA_2_CH21 443 +#define IMX_SC_R_DMA_2_CH22 444 +#define IMX_SC_R_DMA_2_CH23 445 +#define IMX_SC_R_DMA_2_CH24 446 +#define IMX_SC_R_DMA_2_CH25 447 +#define IMX_SC_R_DMA_2_CH26 448 +#define IMX_SC_R_DMA_2_CH27 449 +#define IMX_SC_R_DMA_2_CH28 450 +#define IMX_SC_R_DMA_2_CH29 451 +#define IMX_SC_R_DMA_2_CH30 452 +#define IMX_SC_R_DMA_2_CH31 453 +#define IMX_SC_R_ASRC_1 454 +#define IMX_SC_R_ESAI_1 455 +#define IMX_SC_R_SAI_6 456 +#define IMX_SC_R_SAI_7 457 +#define IMX_SC_R_AMIX 458 +#define IMX_SC_R_MQS_0 459 +#define IMX_SC_R_DMA_3_CH0 460 +#define IMX_SC_R_DMA_3_CH1 461 +#define IMX_SC_R_DMA_3_CH2 462 +#define IMX_SC_R_DMA_3_CH3 463 +#define IMX_SC_R_DMA_3_CH4 464 +#define IMX_SC_R_DMA_3_CH5 465 +#define IMX_SC_R_DMA_3_CH6 466 +#define IMX_SC_R_DMA_3_CH7 467 +#define IMX_SC_R_DMA_3_CH8 468 +#define IMX_SC_R_DMA_3_CH9 469 +#define IMX_SC_R_DMA_3_CH10 470 +#define IMX_SC_R_DMA_3_CH11 471 +#define IMX_SC_R_DMA_3_CH12 472 +#define IMX_SC_R_DMA_3_CH13 473 +#define IMX_SC_R_DMA_3_CH14 474 +#define IMX_SC_R_DMA_3_CH15 475 +#define IMX_SC_R_DMA_3_CH16 476 +#define IMX_SC_R_DMA_3_CH17 477 +#define IMX_SC_R_DMA_3_CH18 478 +#define IMX_SC_R_DMA_3_CH19 479 +#define IMX_SC_R_DMA_3_CH20 480 +#define IMX_SC_R_DMA_3_CH21 481 +#define IMX_SC_R_DMA_3_CH22 482 +#define IMX_SC_R_DMA_3_CH23 483 +#define IMX_SC_R_DMA_3_CH24 484 +#define IMX_SC_R_DMA_3_CH25 485 +#define IMX_SC_R_DMA_3_CH26 486 +#define IMX_SC_R_DMA_3_CH27 487 +#define IMX_SC_R_DMA_3_CH28 488 +#define IMX_SC_R_DMA_3_CH29 489 +#define IMX_SC_R_DMA_3_CH30 490 +#define IMX_SC_R_DMA_3_CH31 491 +#define IMX_SC_R_AUDIO_PLL_1 492 +#define IMX_SC_R_AUDIO_CLK_0 493 +#define IMX_SC_R_AUDIO_CLK_1 494 +#define IMX_SC_R_MCLK_OUT_0 495 +#define IMX_SC_R_MCLK_OUT_1 496 +#define IMX_SC_R_PMIC_0 497 +#define IMX_SC_R_PMIC_1 498 +#define IMX_SC_R_SECO 499 +#define IMX_SC_R_CAAM_JR1 500 +#define IMX_SC_R_CAAM_JR2 501 +#define IMX_SC_R_CAAM_JR3 502 +#define IMX_SC_R_SECO_MU_2 503 +#define IMX_SC_R_SECO_MU_3 504 +#define IMX_SC_R_SECO_MU_4 505 +#define IMX_SC_R_HDMI_RX_PWM_0 506 +#define IMX_SC_R_A35 507 +#define IMX_SC_R_A35_0 508 +#define IMX_SC_R_A35_1 509 +#define IMX_SC_R_A35_2 510 +#define IMX_SC_R_A35_3 511 +#define IMX_SC_R_DSP 512 +#define IMX_SC_R_DSP_RAM 513 +#define IMX_SC_R_CAAM_JR1_OUT 514 +#define IMX_SC_R_CAAM_JR2_OUT 515 +#define IMX_SC_R_CAAM_JR3_OUT 516 +#define IMX_SC_R_VPU_DEC_0 517 +#define IMX_SC_R_VPU_ENC_0 518 +#define IMX_SC_R_CAAM_JR0 519 +#define IMX_SC_R_CAAM_JR0_OUT 520 +#define IMX_SC_R_PMIC_2 521 +#define IMX_SC_R_DBLOGIC 522 +#define IMX_SC_R_HDMI_PLL_1 523 +#define IMX_SC_R_BOARD_R0 524 +#define IMX_SC_R_BOARD_R1 525 +#define IMX_SC_R_BOARD_R2 526 +#define IMX_SC_R_BOARD_R3 527 +#define IMX_SC_R_BOARD_R4 528 +#define IMX_SC_R_BOARD_R5 529 +#define IMX_SC_R_BOARD_R6 530 +#define IMX_SC_R_BOARD_R7 531 +#define IMX_SC_R_MJPEG_DEC_MP 532 +#define IMX_SC_R_MJPEG_ENC_MP 533 +#define IMX_SC_R_VPU_TS_0 534 +#define IMX_SC_R_VPU_MU_0 535 +#define IMX_SC_R_VPU_MU_1 536 +#define IMX_SC_R_VPU_MU_2 537 +#define IMX_SC_R_VPU_MU_3 538 +#define IMX_SC_R_VPU_ENC_1 539 +#define IMX_SC_R_VPU 540 +#define IMX_SC_R_LAST 541 + +#endif /* __DT_BINDINGS_RSCRC_IMX_H */ -- cgit v1.2.3 From 3501ce96bf5d9dd8563dd94595436d3757ec817e Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Thu, 1 Nov 2018 15:19:58 +0000 Subject: firmware: imx: remove resource id enums We already export resource id in dt-bindings headfile which can also be used by drivers. So no need keep the same definitions in regular headfile anymore. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Reviewed-by: Ulf Hansson Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- include/linux/firmware/imx/types.h | 552 ------------------------------------- 1 file changed, 552 deletions(-) (limited to 'include') diff --git a/include/linux/firmware/imx/types.h b/include/linux/firmware/imx/types.h index 9cbf0c4a6069..80821100e85f 100644 --- a/include/linux/firmware/imx/types.h +++ b/include/linux/firmware/imx/types.h @@ -9,558 +9,6 @@ #ifndef _SC_TYPES_H #define _SC_TYPES_H -/* - * This type is used to indicate a resource. Resources include peripherals - * and bus masters (but not memory regions). Note items from list should - * never be changed or removed (only added to at the end of the list). - */ -enum imx_sc_rsrc { - IMX_SC_R_A53 = 0, - IMX_SC_R_A53_0 = 1, - IMX_SC_R_A53_1 = 2, - IMX_SC_R_A53_2 = 3, - IMX_SC_R_A53_3 = 4, - IMX_SC_R_A72 = 5, - IMX_SC_R_A72_0 = 6, - IMX_SC_R_A72_1 = 7, - IMX_SC_R_A72_2 = 8, - IMX_SC_R_A72_3 = 9, - IMX_SC_R_CCI = 10, - IMX_SC_R_DB = 11, - IMX_SC_R_DRC_0 = 12, - IMX_SC_R_DRC_1 = 13, - IMX_SC_R_GIC_SMMU = 14, - IMX_SC_R_IRQSTR_M4_0 = 15, - IMX_SC_R_IRQSTR_M4_1 = 16, - IMX_SC_R_SMMU = 17, - IMX_SC_R_GIC = 18, - IMX_SC_R_DC_0_BLIT0 = 19, - IMX_SC_R_DC_0_BLIT1 = 20, - IMX_SC_R_DC_0_BLIT2 = 21, - IMX_SC_R_DC_0_BLIT_OUT = 22, - IMX_SC_R_DC_0_CAPTURE0 = 23, - IMX_SC_R_DC_0_CAPTURE1 = 24, - IMX_SC_R_DC_0_WARP = 25, - IMX_SC_R_DC_0_INTEGRAL0 = 26, - IMX_SC_R_DC_0_INTEGRAL1 = 27, - IMX_SC_R_DC_0_VIDEO0 = 28, - IMX_SC_R_DC_0_VIDEO1 = 29, - IMX_SC_R_DC_0_FRAC0 = 30, - IMX_SC_R_DC_0_FRAC1 = 31, - IMX_SC_R_DC_0 = 32, - IMX_SC_R_GPU_2_PID0 = 33, - IMX_SC_R_DC_0_PLL_0 = 34, - IMX_SC_R_DC_0_PLL_1 = 35, - IMX_SC_R_DC_1_BLIT0 = 36, - IMX_SC_R_DC_1_BLIT1 = 37, - IMX_SC_R_DC_1_BLIT2 = 38, - IMX_SC_R_DC_1_BLIT_OUT = 39, - IMX_SC_R_DC_1_CAPTURE0 = 40, - IMX_SC_R_DC_1_CAPTURE1 = 41, - IMX_SC_R_DC_1_WARP = 42, - IMX_SC_R_DC_1_INTEGRAL0 = 43, - IMX_SC_R_DC_1_INTEGRAL1 = 44, - IMX_SC_R_DC_1_VIDEO0 = 45, - IMX_SC_R_DC_1_VIDEO1 = 46, - IMX_SC_R_DC_1_FRAC0 = 47, - IMX_SC_R_DC_1_FRAC1 = 48, - IMX_SC_R_DC_1 = 49, - IMX_SC_R_GPU_3_PID0 = 50, - IMX_SC_R_DC_1_PLL_0 = 51, - IMX_SC_R_DC_1_PLL_1 = 52, - IMX_SC_R_SPI_0 = 53, - IMX_SC_R_SPI_1 = 54, - IMX_SC_R_SPI_2 = 55, - IMX_SC_R_SPI_3 = 56, - IMX_SC_R_UART_0 = 57, - IMX_SC_R_UART_1 = 58, - IMX_SC_R_UART_2 = 59, - IMX_SC_R_UART_3 = 60, - IMX_SC_R_UART_4 = 61, - IMX_SC_R_EMVSIM_0 = 62, - IMX_SC_R_EMVSIM_1 = 63, - IMX_SC_R_DMA_0_CH0 = 64, - IMX_SC_R_DMA_0_CH1 = 65, - IMX_SC_R_DMA_0_CH2 = 66, - IMX_SC_R_DMA_0_CH3 = 67, - IMX_SC_R_DMA_0_CH4 = 68, - IMX_SC_R_DMA_0_CH5 = 69, - IMX_SC_R_DMA_0_CH6 = 70, - IMX_SC_R_DMA_0_CH7 = 71, - IMX_SC_R_DMA_0_CH8 = 72, - IMX_SC_R_DMA_0_CH9 = 73, - IMX_SC_R_DMA_0_CH10 = 74, - IMX_SC_R_DMA_0_CH11 = 75, - IMX_SC_R_DMA_0_CH12 = 76, - IMX_SC_R_DMA_0_CH13 = 77, - IMX_SC_R_DMA_0_CH14 = 78, - IMX_SC_R_DMA_0_CH15 = 79, - IMX_SC_R_DMA_0_CH16 = 80, - IMX_SC_R_DMA_0_CH17 = 81, - IMX_SC_R_DMA_0_CH18 = 82, - IMX_SC_R_DMA_0_CH19 = 83, - IMX_SC_R_DMA_0_CH20 = 84, - IMX_SC_R_DMA_0_CH21 = 85, - IMX_SC_R_DMA_0_CH22 = 86, - IMX_SC_R_DMA_0_CH23 = 87, - IMX_SC_R_DMA_0_CH24 = 88, - IMX_SC_R_DMA_0_CH25 = 89, - IMX_SC_R_DMA_0_CH26 = 90, - IMX_SC_R_DMA_0_CH27 = 91, - IMX_SC_R_DMA_0_CH28 = 92, - IMX_SC_R_DMA_0_CH29 = 93, - IMX_SC_R_DMA_0_CH30 = 94, - IMX_SC_R_DMA_0_CH31 = 95, - IMX_SC_R_I2C_0 = 96, - IMX_SC_R_I2C_1 = 97, - IMX_SC_R_I2C_2 = 98, - IMX_SC_R_I2C_3 = 99, - IMX_SC_R_I2C_4 = 100, - IMX_SC_R_ADC_0 = 101, - IMX_SC_R_ADC_1 = 102, - IMX_SC_R_FTM_0 = 103, - IMX_SC_R_FTM_1 = 104, - IMX_SC_R_CAN_0 = 105, - IMX_SC_R_CAN_1 = 106, - IMX_SC_R_CAN_2 = 107, - IMX_SC_R_DMA_1_CH0 = 108, - IMX_SC_R_DMA_1_CH1 = 109, - IMX_SC_R_DMA_1_CH2 = 110, - IMX_SC_R_DMA_1_CH3 = 111, - IMX_SC_R_DMA_1_CH4 = 112, - IMX_SC_R_DMA_1_CH5 = 113, - IMX_SC_R_DMA_1_CH6 = 114, - IMX_SC_R_DMA_1_CH7 = 115, - IMX_SC_R_DMA_1_CH8 = 116, - IMX_SC_R_DMA_1_CH9 = 117, - IMX_SC_R_DMA_1_CH10 = 118, - IMX_SC_R_DMA_1_CH11 = 119, - IMX_SC_R_DMA_1_CH12 = 120, - IMX_SC_R_DMA_1_CH13 = 121, - IMX_SC_R_DMA_1_CH14 = 122, - IMX_SC_R_DMA_1_CH15 = 123, - IMX_SC_R_DMA_1_CH16 = 124, - IMX_SC_R_DMA_1_CH17 = 125, - IMX_SC_R_DMA_1_CH18 = 126, - IMX_SC_R_DMA_1_CH19 = 127, - IMX_SC_R_DMA_1_CH20 = 128, - IMX_SC_R_DMA_1_CH21 = 129, - IMX_SC_R_DMA_1_CH22 = 130, - IMX_SC_R_DMA_1_CH23 = 131, - IMX_SC_R_DMA_1_CH24 = 132, - IMX_SC_R_DMA_1_CH25 = 133, - IMX_SC_R_DMA_1_CH26 = 134, - IMX_SC_R_DMA_1_CH27 = 135, - IMX_SC_R_DMA_1_CH28 = 136, - IMX_SC_R_DMA_1_CH29 = 137, - IMX_SC_R_DMA_1_CH30 = 138, - IMX_SC_R_DMA_1_CH31 = 139, - IMX_SC_R_UNUSED1 = 140, - IMX_SC_R_UNUSED2 = 141, - IMX_SC_R_UNUSED3 = 142, - IMX_SC_R_UNUSED4 = 143, - IMX_SC_R_GPU_0_PID0 = 144, - IMX_SC_R_GPU_0_PID1 = 145, - IMX_SC_R_GPU_0_PID2 = 146, - IMX_SC_R_GPU_0_PID3 = 147, - IMX_SC_R_GPU_1_PID0 = 148, - IMX_SC_R_GPU_1_PID1 = 149, - IMX_SC_R_GPU_1_PID2 = 150, - IMX_SC_R_GPU_1_PID3 = 151, - IMX_SC_R_PCIE_A = 152, - IMX_SC_R_SERDES_0 = 153, - IMX_SC_R_MATCH_0 = 154, - IMX_SC_R_MATCH_1 = 155, - IMX_SC_R_MATCH_2 = 156, - IMX_SC_R_MATCH_3 = 157, - IMX_SC_R_MATCH_4 = 158, - IMX_SC_R_MATCH_5 = 159, - IMX_SC_R_MATCH_6 = 160, - IMX_SC_R_MATCH_7 = 161, - IMX_SC_R_MATCH_8 = 162, - IMX_SC_R_MATCH_9 = 163, - IMX_SC_R_MATCH_10 = 164, - IMX_SC_R_MATCH_11 = 165, - IMX_SC_R_MATCH_12 = 166, - IMX_SC_R_MATCH_13 = 167, - IMX_SC_R_MATCH_14 = 168, - IMX_SC_R_PCIE_B = 169, - IMX_SC_R_SATA_0 = 170, - IMX_SC_R_SERDES_1 = 171, - IMX_SC_R_HSIO_GPIO = 172, - IMX_SC_R_MATCH_15 = 173, - IMX_SC_R_MATCH_16 = 174, - IMX_SC_R_MATCH_17 = 175, - IMX_SC_R_MATCH_18 = 176, - IMX_SC_R_MATCH_19 = 177, - IMX_SC_R_MATCH_20 = 178, - IMX_SC_R_MATCH_21 = 179, - IMX_SC_R_MATCH_22 = 180, - IMX_SC_R_MATCH_23 = 181, - IMX_SC_R_MATCH_24 = 182, - IMX_SC_R_MATCH_25 = 183, - IMX_SC_R_MATCH_26 = 184, - IMX_SC_R_MATCH_27 = 185, - IMX_SC_R_MATCH_28 = 186, - IMX_SC_R_LCD_0 = 187, - IMX_SC_R_LCD_0_PWM_0 = 188, - IMX_SC_R_LCD_0_I2C_0 = 189, - IMX_SC_R_LCD_0_I2C_1 = 190, - IMX_SC_R_PWM_0 = 191, - IMX_SC_R_PWM_1 = 192, - IMX_SC_R_PWM_2 = 193, - IMX_SC_R_PWM_3 = 194, - IMX_SC_R_PWM_4 = 195, - IMX_SC_R_PWM_5 = 196, - IMX_SC_R_PWM_6 = 197, - IMX_SC_R_PWM_7 = 198, - IMX_SC_R_GPIO_0 = 199, - IMX_SC_R_GPIO_1 = 200, - IMX_SC_R_GPIO_2 = 201, - IMX_SC_R_GPIO_3 = 202, - IMX_SC_R_GPIO_4 = 203, - IMX_SC_R_GPIO_5 = 204, - IMX_SC_R_GPIO_6 = 205, - IMX_SC_R_GPIO_7 = 206, - IMX_SC_R_GPT_0 = 207, - IMX_SC_R_GPT_1 = 208, - IMX_SC_R_GPT_2 = 209, - IMX_SC_R_GPT_3 = 210, - IMX_SC_R_GPT_4 = 211, - IMX_SC_R_KPP = 212, - IMX_SC_R_MU_0A = 213, - IMX_SC_R_MU_1A = 214, - IMX_SC_R_MU_2A = 215, - IMX_SC_R_MU_3A = 216, - IMX_SC_R_MU_4A = 217, - IMX_SC_R_MU_5A = 218, - IMX_SC_R_MU_6A = 219, - IMX_SC_R_MU_7A = 220, - IMX_SC_R_MU_8A = 221, - IMX_SC_R_MU_9A = 222, - IMX_SC_R_MU_10A = 223, - IMX_SC_R_MU_11A = 224, - IMX_SC_R_MU_12A = 225, - IMX_SC_R_MU_13A = 226, - IMX_SC_R_MU_5B = 227, - IMX_SC_R_MU_6B = 228, - IMX_SC_R_MU_7B = 229, - IMX_SC_R_MU_8B = 230, - IMX_SC_R_MU_9B = 231, - IMX_SC_R_MU_10B = 232, - IMX_SC_R_MU_11B = 233, - IMX_SC_R_MU_12B = 234, - IMX_SC_R_MU_13B = 235, - IMX_SC_R_ROM_0 = 236, - IMX_SC_R_FSPI_0 = 237, - IMX_SC_R_FSPI_1 = 238, - IMX_SC_R_IEE = 239, - IMX_SC_R_IEE_R0 = 240, - IMX_SC_R_IEE_R1 = 241, - IMX_SC_R_IEE_R2 = 242, - IMX_SC_R_IEE_R3 = 243, - IMX_SC_R_IEE_R4 = 244, - IMX_SC_R_IEE_R5 = 245, - IMX_SC_R_IEE_R6 = 246, - IMX_SC_R_IEE_R7 = 247, - IMX_SC_R_SDHC_0 = 248, - IMX_SC_R_SDHC_1 = 249, - IMX_SC_R_SDHC_2 = 250, - IMX_SC_R_ENET_0 = 251, - IMX_SC_R_ENET_1 = 252, - IMX_SC_R_MLB_0 = 253, - IMX_SC_R_DMA_2_CH0 = 254, - IMX_SC_R_DMA_2_CH1 = 255, - IMX_SC_R_DMA_2_CH2 = 256, - IMX_SC_R_DMA_2_CH3 = 257, - IMX_SC_R_DMA_2_CH4 = 258, - IMX_SC_R_USB_0 = 259, - IMX_SC_R_USB_1 = 260, - IMX_SC_R_USB_0_PHY = 261, - IMX_SC_R_USB_2 = 262, - IMX_SC_R_USB_2_PHY = 263, - IMX_SC_R_DTCP = 264, - IMX_SC_R_NAND = 265, - IMX_SC_R_LVDS_0 = 266, - IMX_SC_R_LVDS_0_PWM_0 = 267, - IMX_SC_R_LVDS_0_I2C_0 = 268, - IMX_SC_R_LVDS_0_I2C_1 = 269, - IMX_SC_R_LVDS_1 = 270, - IMX_SC_R_LVDS_1_PWM_0 = 271, - IMX_SC_R_LVDS_1_I2C_0 = 272, - IMX_SC_R_LVDS_1_I2C_1 = 273, - IMX_SC_R_LVDS_2 = 274, - IMX_SC_R_LVDS_2_PWM_0 = 275, - IMX_SC_R_LVDS_2_I2C_0 = 276, - IMX_SC_R_LVDS_2_I2C_1 = 277, - IMX_SC_R_M4_0_PID0 = 278, - IMX_SC_R_M4_0_PID1 = 279, - IMX_SC_R_M4_0_PID2 = 280, - IMX_SC_R_M4_0_PID3 = 281, - IMX_SC_R_M4_0_PID4 = 282, - IMX_SC_R_M4_0_RGPIO = 283, - IMX_SC_R_M4_0_SEMA42 = 284, - IMX_SC_R_M4_0_TPM = 285, - IMX_SC_R_M4_0_PIT = 286, - IMX_SC_R_M4_0_UART = 287, - IMX_SC_R_M4_0_I2C = 288, - IMX_SC_R_M4_0_INTMUX = 289, - IMX_SC_R_M4_0_SIM = 290, - IMX_SC_R_M4_0_WDOG = 291, - IMX_SC_R_M4_0_MU_0B = 292, - IMX_SC_R_M4_0_MU_0A0 = 293, - IMX_SC_R_M4_0_MU_0A1 = 294, - IMX_SC_R_M4_0_MU_0A2 = 295, - IMX_SC_R_M4_0_MU_0A3 = 296, - IMX_SC_R_M4_0_MU_1A = 297, - IMX_SC_R_M4_1_PID0 = 298, - IMX_SC_R_M4_1_PID1 = 299, - IMX_SC_R_M4_1_PID2 = 300, - IMX_SC_R_M4_1_PID3 = 301, - IMX_SC_R_M4_1_PID4 = 302, - IMX_SC_R_M4_1_RGPIO = 303, - IMX_SC_R_M4_1_SEMA42 = 304, - IMX_SC_R_M4_1_TPM = 305, - IMX_SC_R_M4_1_PIT = 306, - IMX_SC_R_M4_1_UART = 307, - IMX_SC_R_M4_1_I2C = 308, - IMX_SC_R_M4_1_INTMUX = 309, - IMX_SC_R_M4_1_SIM = 310, - IMX_SC_R_M4_1_WDOG = 311, - IMX_SC_R_M4_1_MU_0B = 312, - IMX_SC_R_M4_1_MU_0A0 = 313, - IMX_SC_R_M4_1_MU_0A1 = 314, - IMX_SC_R_M4_1_MU_0A2 = 315, - IMX_SC_R_M4_1_MU_0A3 = 316, - IMX_SC_R_M4_1_MU_1A = 317, - IMX_SC_R_SAI_0 = 318, - IMX_SC_R_SAI_1 = 319, - IMX_SC_R_SAI_2 = 320, - IMX_SC_R_IRQSTR_SCU2 = 321, - IMX_SC_R_IRQSTR_DSP = 322, - IMX_SC_R_UNUSED5 = 323, - IMX_SC_R_UNUSED6 = 324, - IMX_SC_R_AUDIO_PLL_0 = 325, - IMX_SC_R_PI_0 = 326, - IMX_SC_R_PI_0_PWM_0 = 327, - IMX_SC_R_PI_0_PWM_1 = 328, - IMX_SC_R_PI_0_I2C_0 = 329, - IMX_SC_R_PI_0_PLL = 330, - IMX_SC_R_PI_1 = 331, - IMX_SC_R_PI_1_PWM_0 = 332, - IMX_SC_R_PI_1_PWM_1 = 333, - IMX_SC_R_PI_1_I2C_0 = 334, - IMX_SC_R_PI_1_PLL = 335, - IMX_SC_R_SC_PID0 = 336, - IMX_SC_R_SC_PID1 = 337, - IMX_SC_R_SC_PID2 = 338, - IMX_SC_R_SC_PID3 = 339, - IMX_SC_R_SC_PID4 = 340, - IMX_SC_R_SC_SEMA42 = 341, - IMX_SC_R_SC_TPM = 342, - IMX_SC_R_SC_PIT = 343, - IMX_SC_R_SC_UART = 344, - IMX_SC_R_SC_I2C = 345, - IMX_SC_R_SC_MU_0B = 346, - IMX_SC_R_SC_MU_0A0 = 347, - IMX_SC_R_SC_MU_0A1 = 348, - IMX_SC_R_SC_MU_0A2 = 349, - IMX_SC_R_SC_MU_0A3 = 350, - IMX_SC_R_SC_MU_1A = 351, - IMX_SC_R_SYSCNT_RD = 352, - IMX_SC_R_SYSCNT_CMP = 353, - IMX_SC_R_DEBUG = 354, - IMX_SC_R_SYSTEM = 355, - IMX_SC_R_SNVS = 356, - IMX_SC_R_OTP = 357, - IMX_SC_R_VPU_PID0 = 358, - IMX_SC_R_VPU_PID1 = 359, - IMX_SC_R_VPU_PID2 = 360, - IMX_SC_R_VPU_PID3 = 361, - IMX_SC_R_VPU_PID4 = 362, - IMX_SC_R_VPU_PID5 = 363, - IMX_SC_R_VPU_PID6 = 364, - IMX_SC_R_VPU_PID7 = 365, - IMX_SC_R_VPU_UART = 366, - IMX_SC_R_VPUCORE = 367, - IMX_SC_R_VPUCORE_0 = 368, - IMX_SC_R_VPUCORE_1 = 369, - IMX_SC_R_VPUCORE_2 = 370, - IMX_SC_R_VPUCORE_3 = 371, - IMX_SC_R_DMA_4_CH0 = 372, - IMX_SC_R_DMA_4_CH1 = 373, - IMX_SC_R_DMA_4_CH2 = 374, - IMX_SC_R_DMA_4_CH3 = 375, - IMX_SC_R_DMA_4_CH4 = 376, - IMX_SC_R_ISI_CH0 = 377, - IMX_SC_R_ISI_CH1 = 378, - IMX_SC_R_ISI_CH2 = 379, - IMX_SC_R_ISI_CH3 = 380, - IMX_SC_R_ISI_CH4 = 381, - IMX_SC_R_ISI_CH5 = 382, - IMX_SC_R_ISI_CH6 = 383, - IMX_SC_R_ISI_CH7 = 384, - IMX_SC_R_MJPEG_DEC_S0 = 385, - IMX_SC_R_MJPEG_DEC_S1 = 386, - IMX_SC_R_MJPEG_DEC_S2 = 387, - IMX_SC_R_MJPEG_DEC_S3 = 388, - IMX_SC_R_MJPEG_ENC_S0 = 389, - IMX_SC_R_MJPEG_ENC_S1 = 390, - IMX_SC_R_MJPEG_ENC_S2 = 391, - IMX_SC_R_MJPEG_ENC_S3 = 392, - IMX_SC_R_MIPI_0 = 393, - IMX_SC_R_MIPI_0_PWM_0 = 394, - IMX_SC_R_MIPI_0_I2C_0 = 395, - IMX_SC_R_MIPI_0_I2C_1 = 396, - IMX_SC_R_MIPI_1 = 397, - IMX_SC_R_MIPI_1_PWM_0 = 398, - IMX_SC_R_MIPI_1_I2C_0 = 399, - IMX_SC_R_MIPI_1_I2C_1 = 400, - IMX_SC_R_CSI_0 = 401, - IMX_SC_R_CSI_0_PWM_0 = 402, - IMX_SC_R_CSI_0_I2C_0 = 403, - IMX_SC_R_CSI_1 = 404, - IMX_SC_R_CSI_1_PWM_0 = 405, - IMX_SC_R_CSI_1_I2C_0 = 406, - IMX_SC_R_HDMI = 407, - IMX_SC_R_HDMI_I2S = 408, - IMX_SC_R_HDMI_I2C_0 = 409, - IMX_SC_R_HDMI_PLL_0 = 410, - IMX_SC_R_HDMI_RX = 411, - IMX_SC_R_HDMI_RX_BYPASS = 412, - IMX_SC_R_HDMI_RX_I2C_0 = 413, - IMX_SC_R_ASRC_0 = 414, - IMX_SC_R_ESAI_0 = 415, - IMX_SC_R_SPDIF_0 = 416, - IMX_SC_R_SPDIF_1 = 417, - IMX_SC_R_SAI_3 = 418, - IMX_SC_R_SAI_4 = 419, - IMX_SC_R_SAI_5 = 420, - IMX_SC_R_GPT_5 = 421, - IMX_SC_R_GPT_6 = 422, - IMX_SC_R_GPT_7 = 423, - IMX_SC_R_GPT_8 = 424, - IMX_SC_R_GPT_9 = 425, - IMX_SC_R_GPT_10 = 426, - IMX_SC_R_DMA_2_CH5 = 427, - IMX_SC_R_DMA_2_CH6 = 428, - IMX_SC_R_DMA_2_CH7 = 429, - IMX_SC_R_DMA_2_CH8 = 430, - IMX_SC_R_DMA_2_CH9 = 431, - IMX_SC_R_DMA_2_CH10 = 432, - IMX_SC_R_DMA_2_CH11 = 433, - IMX_SC_R_DMA_2_CH12 = 434, - IMX_SC_R_DMA_2_CH13 = 435, - IMX_SC_R_DMA_2_CH14 = 436, - IMX_SC_R_DMA_2_CH15 = 437, - IMX_SC_R_DMA_2_CH16 = 438, - IMX_SC_R_DMA_2_CH17 = 439, - IMX_SC_R_DMA_2_CH18 = 440, - IMX_SC_R_DMA_2_CH19 = 441, - IMX_SC_R_DMA_2_CH20 = 442, - IMX_SC_R_DMA_2_CH21 = 443, - IMX_SC_R_DMA_2_CH22 = 444, - IMX_SC_R_DMA_2_CH23 = 445, - IMX_SC_R_DMA_2_CH24 = 446, - IMX_SC_R_DMA_2_CH25 = 447, - IMX_SC_R_DMA_2_CH26 = 448, - IMX_SC_R_DMA_2_CH27 = 449, - IMX_SC_R_DMA_2_CH28 = 450, - IMX_SC_R_DMA_2_CH29 = 451, - IMX_SC_R_DMA_2_CH30 = 452, - IMX_SC_R_DMA_2_CH31 = 453, - IMX_SC_R_ASRC_1 = 454, - IMX_SC_R_ESAI_1 = 455, - IMX_SC_R_SAI_6 = 456, - IMX_SC_R_SAI_7 = 457, - IMX_SC_R_AMIX = 458, - IMX_SC_R_MQS_0 = 459, - IMX_SC_R_DMA_3_CH0 = 460, - IMX_SC_R_DMA_3_CH1 = 461, - IMX_SC_R_DMA_3_CH2 = 462, - IMX_SC_R_DMA_3_CH3 = 463, - IMX_SC_R_DMA_3_CH4 = 464, - IMX_SC_R_DMA_3_CH5 = 465, - IMX_SC_R_DMA_3_CH6 = 466, - IMX_SC_R_DMA_3_CH7 = 467, - IMX_SC_R_DMA_3_CH8 = 468, - IMX_SC_R_DMA_3_CH9 = 469, - IMX_SC_R_DMA_3_CH10 = 470, - IMX_SC_R_DMA_3_CH11 = 471, - IMX_SC_R_DMA_3_CH12 = 472, - IMX_SC_R_DMA_3_CH13 = 473, - IMX_SC_R_DMA_3_CH14 = 474, - IMX_SC_R_DMA_3_CH15 = 475, - IMX_SC_R_DMA_3_CH16 = 476, - IMX_SC_R_DMA_3_CH17 = 477, - IMX_SC_R_DMA_3_CH18 = 478, - IMX_SC_R_DMA_3_CH19 = 479, - IMX_SC_R_DMA_3_CH20 = 480, - IMX_SC_R_DMA_3_CH21 = 481, - IMX_SC_R_DMA_3_CH22 = 482, - IMX_SC_R_DMA_3_CH23 = 483, - IMX_SC_R_DMA_3_CH24 = 484, - IMX_SC_R_DMA_3_CH25 = 485, - IMX_SC_R_DMA_3_CH26 = 486, - IMX_SC_R_DMA_3_CH27 = 487, - IMX_SC_R_DMA_3_CH28 = 488, - IMX_SC_R_DMA_3_CH29 = 489, - IMX_SC_R_DMA_3_CH30 = 490, - IMX_SC_R_DMA_3_CH31 = 491, - IMX_SC_R_AUDIO_PLL_1 = 492, - IMX_SC_R_AUDIO_CLK_0 = 493, - IMX_SC_R_AUDIO_CLK_1 = 494, - IMX_SC_R_MCLK_OUT_0 = 495, - IMX_SC_R_MCLK_OUT_1 = 496, - IMX_SC_R_PMIC_0 = 497, - IMX_SC_R_PMIC_1 = 498, - IMX_SC_R_SECO = 499, - IMX_SC_R_CAAM_JR1 = 500, - IMX_SC_R_CAAM_JR2 = 501, - IMX_SC_R_CAAM_JR3 = 502, - IMX_SC_R_SECO_MU_2 = 503, - IMX_SC_R_SECO_MU_3 = 504, - IMX_SC_R_SECO_MU_4 = 505, - IMX_SC_R_HDMI_RX_PWM_0 = 506, - IMX_SC_R_A35 = 507, - IMX_SC_R_A35_0 = 508, - IMX_SC_R_A35_1 = 509, - IMX_SC_R_A35_2 = 510, - IMX_SC_R_A35_3 = 511, - IMX_SC_R_DSP = 512, - IMX_SC_R_DSP_RAM = 513, - IMX_SC_R_CAAM_JR1_OUT = 514, - IMX_SC_R_CAAM_JR2_OUT = 515, - IMX_SC_R_CAAM_JR3_OUT = 516, - IMX_SC_R_VPU_DEC_0 = 517, - IMX_SC_R_VPU_ENC_0 = 518, - IMX_SC_R_CAAM_JR0 = 519, - IMX_SC_R_CAAM_JR0_OUT = 520, - IMX_SC_R_PMIC_2 = 521, - IMX_SC_R_DBLOGIC = 522, - IMX_SC_R_HDMI_PLL_1 = 523, - IMX_SC_R_BOARD_R0 = 524, - IMX_SC_R_BOARD_R1 = 525, - IMX_SC_R_BOARD_R2 = 526, - IMX_SC_R_BOARD_R3 = 527, - IMX_SC_R_BOARD_R4 = 528, - IMX_SC_R_BOARD_R5 = 529, - IMX_SC_R_BOARD_R6 = 530, - IMX_SC_R_BOARD_R7 = 531, - IMX_SC_R_MJPEG_DEC_MP = 532, - IMX_SC_R_MJPEG_ENC_MP = 533, - IMX_SC_R_VPU_TS_0 = 534, - IMX_SC_R_VPU_MU_0 = 535, - IMX_SC_R_VPU_MU_1 = 536, - IMX_SC_R_VPU_MU_2 = 537, - IMX_SC_R_VPU_MU_3 = 538, - IMX_SC_R_VPU_ENC_1 = 539, - IMX_SC_R_VPU = 540, - IMX_SC_R_LAST -}; - -/* NOTE - please add by replacing some of the UNUSED from above! */ - /* * This type is used to indicate a control. */ -- cgit v1.2.3 From 0a914a4948d4604c08750ae67dc33f8b5702402f Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Thu, 1 Nov 2018 15:20:08 +0000 Subject: firmware: imx: add pm svc headfile Add SCU PM SVC related protocol definitions which will be used by a number of PM functions like Power Domain, Clock, Reset and etc. The detailed implementation of each function will put in the individual function drivers. Cc: Shawn Guo Cc: Sascha Hauer Reviewed-by: Ulf Hansson Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- include/linux/firmware/imx/sci.h | 1 + include/linux/firmware/imx/svc/pm.h | 85 +++++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+) create mode 100644 include/linux/firmware/imx/svc/pm.h (limited to 'include') diff --git a/include/linux/firmware/imx/sci.h b/include/linux/firmware/imx/sci.h index 29ada609de03..ebc55098faee 100644 --- a/include/linux/firmware/imx/sci.h +++ b/include/linux/firmware/imx/sci.h @@ -14,4 +14,5 @@ #include #include +#include #endif /* _SC_SCI_H */ diff --git a/include/linux/firmware/imx/svc/pm.h b/include/linux/firmware/imx/svc/pm.h new file mode 100644 index 000000000000..1f6975dd37b0 --- /dev/null +++ b/include/linux/firmware/imx/svc/pm.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * Header file containing the public API for the System Controller (SC) + * Power Management (PM) function. This includes functions for power state + * control, clock control, reset control, and wake-up event control. + * + * PM_SVC (SVC) Power Management Service + * + * Module for the Power Management (PM) service. + */ + +#ifndef _SC_PM_API_H +#define _SC_PM_API_H + +#include + +/* + * This type is used to indicate RPC PM function calls. + */ +enum imx_sc_pm_func { + IMX_SC_PM_FUNC_UNKNOWN = 0, + IMX_SC_PM_FUNC_SET_SYS_POWER_MODE = 19, + IMX_SC_PM_FUNC_SET_PARTITION_POWER_MODE = 1, + IMX_SC_PM_FUNC_GET_SYS_POWER_MODE = 2, + IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE = 3, + IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE = 4, + IMX_SC_PM_FUNC_REQ_LOW_POWER_MODE = 16, + IMX_SC_PM_FUNC_SET_CPU_RESUME_ADDR = 17, + IMX_SC_PM_FUNC_REQ_SYS_IF_POWER_MODE = 18, + IMX_SC_PM_FUNC_SET_CLOCK_RATE = 5, + IMX_SC_PM_FUNC_GET_CLOCK_RATE = 6, + IMX_SC_PM_FUNC_CLOCK_ENABLE = 7, + IMX_SC_PM_FUNC_SET_CLOCK_PARENT = 14, + IMX_SC_PM_FUNC_GET_CLOCK_PARENT = 15, + IMX_SC_PM_FUNC_RESET = 13, + IMX_SC_PM_FUNC_RESET_REASON = 10, + IMX_SC_PM_FUNC_BOOT = 8, + IMX_SC_PM_FUNC_REBOOT = 9, + IMX_SC_PM_FUNC_REBOOT_PARTITION = 12, + IMX_SC_PM_FUNC_CPU_START = 11, +}; + +/* + * Defines for ALL parameters + */ +#define IMX_SC_PM_CLK_ALL UINT8_MAX /* All clocks */ + +/* + * Defines for SC PM Power Mode + */ +#define IMX_SC_PM_PW_MODE_OFF 0 /* Power off */ +#define IMX_SC_PM_PW_MODE_STBY 1 /* Power in standby */ +#define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */ +#define IMX_SC_PM_PW_MODE_ON 3 /* Power on */ + +/* + * Defines for SC PM CLK + */ +#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ +#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ +#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ +#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ +#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ +#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ +#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ +#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ +#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ +#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ +#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ +#define IMX_SC_PM_CLK_PLL 4 /* PLL */ +#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ + +/* + * Defines for SC PM CLK Parent + */ +#define IMX_SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */ +#define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */ +#define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */ +#define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */ +#define IMX_SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */ + +#endif /* _SC_PM_API_H */ -- cgit v1.2.3 From c4fe17e0e3a346cc855b7b41c00ff7b04c56d32b Mon Sep 17 00:00:00 2001 From: Arun Kumar Neelakantam Date: Wed, 3 Oct 2018 11:10:02 +0530 Subject: soc: qcom: qmi_interface: Limit txn ids to U16_MAX Txn IDs created up to INT_MAX cause overflow while storing the IDs in u16 type supported by QMI header. Limit the txn IDs max value to U16_MAX to avoid overflow. Signed-off-by: Arun Kumar Neelakantam Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- drivers/soc/qcom/qmi_interface.c | 2 +- include/linux/soc/qcom/qmi.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c index 938ca41c56cd..c239a28e503f 100644 --- a/drivers/soc/qcom/qmi_interface.c +++ b/drivers/soc/qcom/qmi_interface.c @@ -318,7 +318,7 @@ int qmi_txn_init(struct qmi_handle *qmi, struct qmi_txn *txn, txn->dest = c_struct; mutex_lock(&qmi->txn_lock); - ret = idr_alloc_cyclic(&qmi->txns, txn, 0, INT_MAX, GFP_KERNEL); + ret = idr_alloc_cyclic(&qmi->txns, txn, 0, U16_MAX, GFP_KERNEL); if (ret < 0) pr_err("failed to allocate transaction id\n"); diff --git a/include/linux/soc/qcom/qmi.h b/include/linux/soc/qcom/qmi.h index f4de33654a60..5efa2b67fa55 100644 --- a/include/linux/soc/qcom/qmi.h +++ b/include/linux/soc/qcom/qmi.h @@ -166,7 +166,7 @@ struct qmi_ops { struct qmi_txn { struct qmi_handle *qmi; - int id; + u16 id; struct mutex lock; struct completion completion; -- cgit v1.2.3 From ed3cafa79ea756be653d22087c017af95ea78a49 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 26 Sep 2018 11:02:34 -0700 Subject: soc: qcom: cmd-db: Stop memcpy()ing in cmd_db_read_aux_data() Let's change the function signature to return the pointer to memory or an error pointer on failure, and take an argument that lets us return the size of the aux data read. This way we can remove the cmd_db_read_aux_data_len() API entirely and also get rid of the memcpy operation from cmd_db to the caller. Updating the only user of this code shows that making this change allows us to remove a function and put the lookup where the user is. Cc: Mahesh Sivasubramanian Cc: Lina Iyer Cc: Bjorn Andersson Cc: Evan Green Cc: Jordan Crouse Cc: Rob Clark Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 54 ++++++++++++----------------------- drivers/soc/qcom/cmd-db.c | 43 ++++++---------------------- include/soc/qcom/cmd-db.h | 12 ++------ 3 files changed, 30 insertions(+), 79 deletions(-) (limited to 'include') diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index d4e98e5876bc..546599a7ab05 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -902,26 +902,6 @@ static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) return ret; } -/* Get the list of RPMh voltage levels from cmd-db */ -static int a6xx_gmu_rpmh_arc_cmds(const char *id, void *vals, int size) -{ - u32 len = cmd_db_read_aux_data_len(id); - - if (!len) - return 0; - - if (WARN_ON(len > size)) - return -EINVAL; - - cmd_db_read_aux_data(id, vals, len); - - /* - * The data comes back as an array of unsigned shorts so adjust the - * count accordingly - */ - return len >> 1; -} - /* Return the 'arc-level' for the given frequency */ static u32 a6xx_gmu_get_arc_level(struct device *dev, unsigned long freq) { @@ -949,11 +929,25 @@ static u32 a6xx_gmu_get_arc_level(struct device *dev, unsigned long freq) } static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, - unsigned long *freqs, int freqs_count, - u16 *pri, int pri_count, - u16 *sec, int sec_count) + unsigned long *freqs, int freqs_count, const char *id) { int i, j; + const u16 *pri, *sec; + size_t pri_count, sec_count; + + pri = cmd_db_read_aux_data(id, &pri_count); + /* + * The data comes back as an array of unsigned shorts so adjust the + * count accordingly + */ + pri_count >>= 1; + if (!pri_count) + return -EINVAL; + + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); + sec_count >>= 1; + if (!sec_count) + return -EINVAL; /* Construct a vote for each frequency */ for (i = 0; i < freqs_count; i++) { @@ -1012,25 +1006,15 @@ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct msm_gpu *gpu = &adreno_gpu->base; - - u16 gx[16], cx[16], mx[16]; - u32 gxcount, cxcount, mxcount; int ret; - /* Get the list of available voltage levels for each component */ - gxcount = a6xx_gmu_rpmh_arc_cmds("gfx.lvl", gx, sizeof(gx)); - cxcount = a6xx_gmu_rpmh_arc_cmds("cx.lvl", cx, sizeof(cx)); - mxcount = a6xx_gmu_rpmh_arc_cmds("mx.lvl", mx, sizeof(mx)); - /* Build the GX votes */ ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, - gmu->gpu_freqs, gmu->nr_gpu_freqs, - gx, gxcount, mx, mxcount); + gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); /* Build the CX votes */ ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, - gmu->gmu_freqs, gmu->nr_gmu_freqs, - cx, cxcount, mx, mxcount); + gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); return ret; } diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c index 5c9cc6824891..c701b3b010f1 100644 --- a/drivers/soc/qcom/cmd-db.c +++ b/drivers/soc/qcom/cmd-db.c @@ -192,55 +192,28 @@ EXPORT_SYMBOL(cmd_db_read_addr); /** * cmd_db_read_aux_data() - Query command db for aux data. * - * @id: Resource to retrieve AUX Data on. - * @data: Data buffer to copy returned aux data to. Returns size on NULL - * @len: Caller provides size of data buffer passed in. + * @id: Resource to retrieve AUX Data on + * @len: size of data buffer returned * - * Return: size of data on success, errno otherwise + * Return: pointer to data on success, error pointer otherwise */ -int cmd_db_read_aux_data(const char *id, u8 *data, size_t len) +const void *cmd_db_read_aux_data(const char *id, size_t *len) { int ret; const struct entry_header *ent; const struct rsc_hdr *rsc_hdr; - u16 ent_len; - - if (!data) - return -EINVAL; ret = cmd_db_get_header(id, &ent, &rsc_hdr); if (ret) - return ret; - - ent_len = le16_to_cpu(ent->len); - if (len < ent_len) - return -EINVAL; + return ERR_PTR(ret); - len = min_t(u16, ent_len, len); - memcpy(data, rsc_offset(rsc_hdr, ent), len); + if (len) + *len = le16_to_cpu(ent->len); - return len; + return rsc_offset(rsc_hdr, ent); } EXPORT_SYMBOL(cmd_db_read_aux_data); -/** - * cmd_db_read_aux_data_len - Get the length of the auxiliary data stored in DB. - * - * @id: Resource to retrieve AUX Data. - * - * Return: size on success, 0 on error - */ -size_t cmd_db_read_aux_data_len(const char *id) -{ - int ret; - const struct entry_header *ent; - - ret = cmd_db_get_header(id, &ent, NULL); - - return ret < 0 ? 0 : le16_to_cpu(ent->len); -} -EXPORT_SYMBOL(cmd_db_read_aux_data_len); - /** * cmd_db_read_slave_id - Get the slave ID for a given resource address * diff --git a/include/soc/qcom/cmd-db.h b/include/soc/qcom/cmd-db.h index 578180cbc134..af9722223925 100644 --- a/include/soc/qcom/cmd-db.h +++ b/include/soc/qcom/cmd-db.h @@ -18,9 +18,7 @@ enum cmd_db_hw_type { #if IS_ENABLED(CONFIG_QCOM_COMMAND_DB) u32 cmd_db_read_addr(const char *resource_id); -int cmd_db_read_aux_data(const char *resource_id, u8 *data, size_t len); - -size_t cmd_db_read_aux_data_len(const char *resource_id); +const void *cmd_db_read_aux_data(const char *resource_id, size_t *len); enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id); @@ -29,12 +27,8 @@ int cmd_db_ready(void); static inline u32 cmd_db_read_addr(const char *resource_id) { return 0; } -static inline int cmd_db_read_aux_data(const char *resource_id, u8 *data, - size_t len) -{ return -ENODEV; } - -static inline size_t cmd_db_read_aux_data_len(const char *resource_id) -{ return -ENODEV; } +static inline const void *cmd_db_read_aux_data(const char *resource_id, size_t *len) +{ return ERR_PTR(-ENODEV); } static inline enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id) { return -ENODEV; } -- cgit v1.2.3 From bb661b70883717154e194cad544e2b9c25895268 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Mon, 22 Oct 2018 22:35:02 +0200 Subject: soc: bcm: Switch raspberrypi-power to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Cc: Alexander Aring Cc: Eric Anholt Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- drivers/soc/bcm/raspberrypi-power.c | 5 +---- include/dt-bindings/power/raspberrypi-power.h | 5 +---- 2 files changed, 2 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/drivers/soc/bcm/raspberrypi-power.c b/drivers/soc/bcm/raspberrypi-power.c index a78dfe0a2b50..5d1aacdd84ef 100644 --- a/drivers/soc/bcm/raspberrypi-power.c +++ b/drivers/soc/bcm/raspberrypi-power.c @@ -1,8 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 /* (C) 2015 Pengutronix, Alexander Aring - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. * * Authors: * Alexander Aring diff --git a/include/dt-bindings/power/raspberrypi-power.h b/include/dt-bindings/power/raspberrypi-power.h index b3ff8e09a78f..3575f9f4b0bd 100644 --- a/include/dt-bindings/power/raspberrypi-power.h +++ b/include/dt-bindings/power/raspberrypi-power.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright © 2015 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H -- cgit v1.2.3 From 502b431cda801645fd73857f7b47a4666de3cb62 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Mon, 22 Oct 2018 22:26:24 +0200 Subject: firmware: raspberrypi: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Cc: Eric Anholt Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- drivers/firmware/raspberrypi.c | 5 +---- include/soc/bcm2835/raspberrypi-firmware.h | 5 +---- 2 files changed, 2 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/drivers/firmware/raspberrypi.c b/drivers/firmware/raspberrypi.c index d3f7d1434657..a13558154ac3 100644 --- a/drivers/firmware/raspberrypi.c +++ b/drivers/firmware/raspberrypi.c @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Defines interfaces for interacting wtih the Raspberry Pi firmware's * property channel. * * Copyright © 2015 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include diff --git a/include/soc/bcm2835/raspberrypi-firmware.h b/include/soc/bcm2835/raspberrypi-firmware.h index c4a5c9e9fb47..4be1aa4435ae 100644 --- a/include/soc/bcm2835/raspberrypi-firmware.h +++ b/include/soc/bcm2835/raspberrypi-firmware.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright © 2015 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __SOC_RASPBERRY_FIRMWARE_H__ -- cgit v1.2.3 From eac9c48aac0822c2621aa6f3a03b501cd6524bf6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 25 Jan 2018 14:43:45 +0200 Subject: soc/tegra: pmc: Add Tegra194 support The PMC controller on Tegra194 has a couple of new I/O pads and drops others compared to Tegra186. Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++- include/soc/tegra/pmc.h | 21 ++++++++++++++++ 2 files changed, 86 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index a4276f6bc8a3..6bf1abe73df7 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -2233,8 +2233,72 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .num_reset_levels = 3, }; +static const struct tegra_io_pad_soc tegra194_io_pads[] = { + { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, +}; + +static const struct tegra_pmc_soc tegra194_pmc_soc = { + .num_powergates = 0, + .powergates = NULL, + .num_cpu_powergates = 0, + .cpu_powergates = NULL, + .has_tsense_reset = false, + .has_gpu_clamps = false, + .num_io_pads = ARRAY_SIZE(tegra194_io_pads), + .io_pads = tegra194_io_pads, + .regs = &tegra186_pmc_regs, + .init = NULL, + .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, +}; + static const struct of_device_id tegra_pmc_match[] = { - { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc }, + { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index 562426812ab2..fd816f6aa9cc 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -90,6 +90,10 @@ enum tegra_io_pad { TEGRA_IO_PAD_CSID, TEGRA_IO_PAD_CSIE, TEGRA_IO_PAD_CSIF, + TEGRA_IO_PAD_CSIG, + TEGRA_IO_PAD_CSIH, + TEGRA_IO_PAD_DAP3, + TEGRA_IO_PAD_DAP5, TEGRA_IO_PAD_DBG, TEGRA_IO_PAD_DEBUG_NONAO, TEGRA_IO_PAD_DMIC, @@ -102,10 +106,15 @@ enum tegra_io_pad { TEGRA_IO_PAD_EDP, TEGRA_IO_PAD_EMMC, TEGRA_IO_PAD_EMMC2, + TEGRA_IO_PAD_EQOS, TEGRA_IO_PAD_GPIO, + TEGRA_IO_PAD_GP_PWM2, + TEGRA_IO_PAD_GP_PWM3, TEGRA_IO_PAD_HDMI, TEGRA_IO_PAD_HDMI_DP0, TEGRA_IO_PAD_HDMI_DP1, + TEGRA_IO_PAD_HDMI_DP2, + TEGRA_IO_PAD_HDMI_DP3, TEGRA_IO_PAD_HSIC, TEGRA_IO_PAD_HV, TEGRA_IO_PAD_LVDS, @@ -115,8 +124,14 @@ enum tegra_io_pad { TEGRA_IO_PAD_PEX_CLK_BIAS, TEGRA_IO_PAD_PEX_CLK1, TEGRA_IO_PAD_PEX_CLK2, + TEGRA_IO_PAD_PEX_CLK2_BIAS, TEGRA_IO_PAD_PEX_CLK3, TEGRA_IO_PAD_PEX_CNTRL, + TEGRA_IO_PAD_PEX_CTL2, + TEGRA_IO_PAD_PEX_L0_RST_N, + TEGRA_IO_PAD_PEX_L1_RST_N, + TEGRA_IO_PAD_PEX_L5_RST_N, + TEGRA_IO_PAD_PWR_CTL, TEGRA_IO_PAD_SDMMC1, TEGRA_IO_PAD_SDMMC1_HV, TEGRA_IO_PAD_SDMMC2, @@ -124,10 +139,16 @@ enum tegra_io_pad { TEGRA_IO_PAD_SDMMC3, TEGRA_IO_PAD_SDMMC3_HV, TEGRA_IO_PAD_SDMMC4, + TEGRA_IO_PAD_SOC_GPIO10, + TEGRA_IO_PAD_SOC_GPIO12, + TEGRA_IO_PAD_SOC_GPIO13, + TEGRA_IO_PAD_SOC_GPIO53, TEGRA_IO_PAD_SPI, TEGRA_IO_PAD_SPI_HV, TEGRA_IO_PAD_SYS_DDC, TEGRA_IO_PAD_UART, + TEGRA_IO_PAD_UART4, + TEGRA_IO_PAD_UART5, TEGRA_IO_PAD_UFS, TEGRA_IO_PAD_USB0, TEGRA_IO_PAD_USB1, -- cgit v1.2.3 From da3e1c57caf93ed379f14686e877f806111abe7c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 29 Nov 2018 11:56:15 +0100 Subject: soc: renesas: r8a77970-sysc: Remove non-existent CR7 power domain The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) removed the CR7 power domain on R-Car V3M, as this SoC does not have an ARM Cortex-R7 Realtime Core. As this definition was never used from DT, it can just be removed. Fixes: 833bdb47c826a1a6 ("dt-bindings: power: add R8A77970 SYSC power domain definitions") Fixes: bab9b2a74fe9da96 ("soc: renesas: rcar-sysc: add R8A77970 support") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- drivers/soc/renesas/r8a77970-sysc.c | 1 - include/dt-bindings/power/r8a77970-sysc.h | 1 - 2 files changed, 2 deletions(-) (limited to 'include') diff --git a/drivers/soc/renesas/r8a77970-sysc.c b/drivers/soc/renesas/r8a77970-sysc.c index 35b30d6a8958..2c6d76490ca0 100644 --- a/drivers/soc/renesas/r8a77970-sysc.c +++ b/drivers/soc/renesas/r8a77970-sysc.c @@ -20,7 +20,6 @@ static const struct rcar_sysc_area r8a77970_areas[] __initconst = { PD_CPU_NOCR }, { "ca53-cpu1", 0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU, PD_CPU_NOCR }, - { "cr7", 0x240, 0, R8A77970_PD_CR7, R8A77970_PD_ALWAYS_ON }, { "a3ir", 0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON }, { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_A3IR }, { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A3IR }, diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h index bf54779d1625..5c1ef1398b70 100644 --- a/include/dt-bindings/power/r8a77970-sysc.h +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -16,7 +16,6 @@ #define R8A77970_PD_CA53_CPU0 5 #define R8A77970_PD_CA53_CPU1 6 -#define R8A77970_PD_CR7 13 #define R8A77970_PD_CA53_SCU 21 #define R8A77970_PD_A2IR0 23 #define R8A77970_PD_A3IR 24 -- cgit v1.2.3 From b5eb730e031acaba2d25e8f522ac5966a70885ae Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 29 Nov 2018 11:56:16 +0100 Subject: soc: renesas: r8a77970-sysc: Correct names of A2DP/A2CN power domains The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A2IR2 and A2IR3 power domains on R-Car V3M to A2DP resp. A2CN. As these definitions are not yet used from DT, they can just be renamed. While at it, fix the indentation of the A3IR definition. Fixes: 833bdb47c826a1a6 ("dt-bindings: power: add R8A77970 SYSC power domain definitions") Fixes: bab9b2a74fe9da96 ("soc: renesas: rcar-sysc: add R8A77970 support") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- drivers/soc/renesas/r8a77970-sysc.c | 4 ++-- include/dt-bindings/power/r8a77970-sysc.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/soc/renesas/r8a77970-sysc.c b/drivers/soc/renesas/r8a77970-sysc.c index 2c6d76490ca0..280c48b80f24 100644 --- a/drivers/soc/renesas/r8a77970-sysc.c +++ b/drivers/soc/renesas/r8a77970-sysc.c @@ -23,8 +23,8 @@ static const struct rcar_sysc_area r8a77970_areas[] __initconst = { { "a3ir", 0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON }, { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_A3IR }, { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A3IR }, - { "a2ir2", 0x400, 2, R8A77970_PD_A2IR2, R8A77970_PD_A3IR }, - { "a2ir3", 0x400, 3, R8A77970_PD_A2IR3, R8A77970_PD_A3IR }, + { "a2dp", 0x400, 2, R8A77970_PD_A2DP, R8A77970_PD_A3IR }, + { "a2cn", 0x400, 3, R8A77970_PD_A2CN, R8A77970_PD_A3IR }, { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_A3IR }, { "a2sc1", 0x400, 5, R8A77970_PD_A2SC1, R8A77970_PD_A3IR }, }; diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h index 5c1ef1398b70..85cc5f23cf9f 100644 --- a/include/dt-bindings/power/r8a77970-sysc.h +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -18,10 +18,10 @@ #define R8A77970_PD_CA53_CPU1 6 #define R8A77970_PD_CA53_SCU 21 #define R8A77970_PD_A2IR0 23 -#define R8A77970_PD_A3IR 24 +#define R8A77970_PD_A3IR 24 #define R8A77970_PD_A2IR1 27 -#define R8A77970_PD_A2IR2 28 -#define R8A77970_PD_A2IR3 29 +#define R8A77970_PD_A2DP 28 +#define R8A77970_PD_A2CN 29 #define R8A77970_PD_A2SC0 30 #define R8A77970_PD_A2SC1 31 -- cgit v1.2.3 From 97473bc85b22ac610b1810b6a9a4669a6cb0b7b0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 29 Nov 2018 11:56:17 +0100 Subject: soc: renesas: r8a77980-sysc: Correct names of A2DP[01] power domains The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A2PD0 and A2DP0 power domains on R-Car V3H to A2DP0 resp. A2DP1. As these definitions are not yet used from DT, they can just be renamed. Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain definitions") Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- drivers/soc/renesas/r8a77980-sysc.c | 4 ++-- include/dt-bindings/power/r8a77980-sysc.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/soc/renesas/r8a77980-sysc.c b/drivers/soc/renesas/r8a77980-sysc.c index 9265fb525ef3..dbb2621ce4e3 100644 --- a/drivers/soc/renesas/r8a77980-sysc.c +++ b/drivers/soc/renesas/r8a77980-sysc.c @@ -38,8 +38,8 @@ static const struct rcar_sysc_area r8a77980_areas[] __initconst = { { "a2sc2", 0x400, 8, R8A77980_PD_A2SC2, R8A77980_PD_A3IR }, { "a2sc3", 0x400, 9, R8A77980_PD_A2SC3, R8A77980_PD_A3IR }, { "a2sc4", 0x400, 10, R8A77980_PD_A2SC4, R8A77980_PD_A3IR }, - { "a2pd0", 0x400, 11, R8A77980_PD_A2PD0, R8A77980_PD_A3IR }, - { "a2pd1", 0x400, 12, R8A77980_PD_A2PD1, R8A77980_PD_A3IR }, + { "a2dp0", 0x400, 11, R8A77980_PD_A2DP0, R8A77980_PD_A3IR }, + { "a2dp1", 0x400, 12, R8A77980_PD_A2DP1, R8A77980_PD_A3IR }, { "a2cn", 0x400, 13, R8A77980_PD_A2CN, R8A77980_PD_A3IR }, { "a3vip", 0x2c0, 0, R8A77980_PD_A3VIP, R8A77980_PD_ALWAYS_ON }, { "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1, R8A77980_PD_A3VIP }, diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h index 2c90c1237725..7bebe7e8dbdb 100644 --- a/include/dt-bindings/power/r8a77980-sysc.h +++ b/include/dt-bindings/power/r8a77980-sysc.h @@ -15,8 +15,8 @@ #define R8A77980_PD_A2SC2 0 #define R8A77980_PD_A2SC3 1 #define R8A77980_PD_A2SC4 2 -#define R8A77980_PD_A2PD0 3 -#define R8A77980_PD_A2PD1 4 +#define R8A77980_PD_A2DP0 3 +#define R8A77980_PD_A2DP1 4 #define R8A77980_PD_CA53_CPU0 5 #define R8A77980_PD_CA53_CPU1 6 #define R8A77980_PD_CA53_CPU2 7 -- cgit v1.2.3 From 160bfa7c724b348a90a12dd9694f351927a15b8e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 29 Nov 2018 11:56:18 +0100 Subject: soc: renesas: r8a77980-sysc: Correct A3VIP[012] power domain hierarchy The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A3VIP power domain on R-Car V3H to A3VIP0, and clarified the power domain hierarchy for the A3VIP[012] power domains. As the definition for the A3VIP0 domain is not yet used from DT, it can just be renamed. Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain definitions") Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- drivers/soc/renesas/r8a77980-sysc.c | 6 +++--- include/dt-bindings/power/r8a77980-sysc.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/soc/renesas/r8a77980-sysc.c b/drivers/soc/renesas/r8a77980-sysc.c index dbb2621ce4e3..a8dbe55e8ba8 100644 --- a/drivers/soc/renesas/r8a77980-sysc.c +++ b/drivers/soc/renesas/r8a77980-sysc.c @@ -41,9 +41,9 @@ static const struct rcar_sysc_area r8a77980_areas[] __initconst = { { "a2dp0", 0x400, 11, R8A77980_PD_A2DP0, R8A77980_PD_A3IR }, { "a2dp1", 0x400, 12, R8A77980_PD_A2DP1, R8A77980_PD_A3IR }, { "a2cn", 0x400, 13, R8A77980_PD_A2CN, R8A77980_PD_A3IR }, - { "a3vip", 0x2c0, 0, R8A77980_PD_A3VIP, R8A77980_PD_ALWAYS_ON }, - { "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1, R8A77980_PD_A3VIP }, - { "a3vip2", 0x280, 0, R8A77980_PD_A3VIP2, R8A77980_PD_A3VIP }, + { "a3vip0", 0x2c0, 0, R8A77980_PD_A3VIP0, R8A77980_PD_ALWAYS_ON }, + { "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1, R8A77980_PD_ALWAYS_ON }, + { "a3vip2", 0x280, 0, R8A77980_PD_A3VIP2, R8A77980_PD_ALWAYS_ON }, }; const struct rcar_sysc_info r8a77980_sysc_info __initconst = { diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h index 7bebe7e8dbdb..e12c8587b87e 100644 --- a/include/dt-bindings/power/r8a77980-sysc.h +++ b/include/dt-bindings/power/r8a77980-sysc.h @@ -22,7 +22,7 @@ #define R8A77980_PD_CA53_CPU2 7 #define R8A77980_PD_CA53_CPU3 8 #define R8A77980_PD_A2CN 10 -#define R8A77980_PD_A3VIP 11 +#define R8A77980_PD_A3VIP0 11 #define R8A77980_PD_A2IR5 12 #define R8A77980_PD_CR7 13 #define R8A77980_PD_A2IR4 15 -- cgit v1.2.3 From 576f1b4bc80220e1f88f1de5ecb25d99a6e9fa04 Mon Sep 17 00:00:00 2001 From: Houlong Wei Date: Thu, 29 Nov 2018 11:37:09 +0800 Subject: soc: mediatek: Add Mediatek CMDQ helper Add Mediatek CMDQ helper to create CMDQ packet and assemble GCE op code. Signed-off-by: Houlong Wei Signed-off-by: HS Liao Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/Kconfig | 12 ++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-cmdq-helper.c | 300 +++++++++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 133 +++++++++++++++ 4 files changed, 446 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-cmdq-helper.c create mode 100644 include/linux/soc/mediatek/mtk-cmdq.h (limited to 'include') diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index a7d0667338f2..17bd7590464f 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -4,6 +4,18 @@ menu "MediaTek SoC drivers" depends on ARCH_MEDIATEK || COMPILE_TEST +config MTK_CMDQ + tristate "MediaTek CMDQ Support" + depends on ARCH_MEDIATEK || COMPILE_TEST + select MAILBOX + select MTK_CMDQ_MBOX + select MTK_INFRACFG + help + Say yes here to add support for the MediaTek Command Queue (CMDQ) + driver. The CMDQ is used to help read/write registers with critical + time limitation, such as updating display configuration during the + vblank. + config MTK_INFRACFG bool "MediaTek INFRACFG Support" select REGMAP diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 12998b08819e..64ce5eeaba32 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c new file mode 100644 index 000000000000..ff9fef5a032b --- /dev/null +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2018 MediaTek Inc. + +#include +#include +#include +#include +#include +#include + +#define CMDQ_ARG_A_WRITE_MASK 0xffff +#define CMDQ_WRITE_ENABLE_MASK BIT(0) +#define CMDQ_EOC_IRQ_EN BIT(0) +#define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \ + << 32 | CMDQ_EOC_IRQ_EN) + +static void cmdq_client_timeout(struct timer_list *t) +{ + struct cmdq_client *client = from_timer(client, t, timer); + + dev_err(client->client.dev, "cmdq timeout!\n"); +} + +struct cmdq_client *cmdq_mbox_create(struct device *dev, int index, u32 timeout) +{ + struct cmdq_client *client; + + client = kzalloc(sizeof(*client), GFP_KERNEL); + if (!client) + return (struct cmdq_client *)-ENOMEM; + + client->timeout_ms = timeout; + if (timeout != CMDQ_NO_TIMEOUT) { + spin_lock_init(&client->lock); + timer_setup(&client->timer, cmdq_client_timeout, 0); + } + client->pkt_cnt = 0; + client->client.dev = dev; + client->client.tx_block = false; + client->chan = mbox_request_channel(&client->client, index); + + if (IS_ERR(client->chan)) { + long err; + + dev_err(dev, "failed to request channel\n"); + err = PTR_ERR(client->chan); + kfree(client); + + return ERR_PTR(err); + } + + return client; +} +EXPORT_SYMBOL(cmdq_mbox_create); + +void cmdq_mbox_destroy(struct cmdq_client *client) +{ + if (client->timeout_ms != CMDQ_NO_TIMEOUT) { + spin_lock(&client->lock); + del_timer_sync(&client->timer); + spin_unlock(&client->lock); + } + mbox_free_channel(client->chan); + kfree(client); +} +EXPORT_SYMBOL(cmdq_mbox_destroy); + +struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size) +{ + struct cmdq_pkt *pkt; + struct device *dev; + dma_addr_t dma_addr; + + pkt = kzalloc(sizeof(*pkt), GFP_KERNEL); + if (!pkt) + return ERR_PTR(-ENOMEM); + pkt->va_base = kzalloc(size, GFP_KERNEL); + if (!pkt->va_base) { + kfree(pkt); + return ERR_PTR(-ENOMEM); + } + pkt->buf_size = size; + pkt->cl = (void *)client; + + dev = client->chan->mbox->dev; + dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size, + DMA_TO_DEVICE); + if (dma_mapping_error(dev, dma_addr)) { + dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size); + kfree(pkt->va_base); + kfree(pkt); + return ERR_PTR(-ENOMEM); + } + + pkt->pa_base = dma_addr; + + return pkt; +} +EXPORT_SYMBOL(cmdq_pkt_create); + +void cmdq_pkt_destroy(struct cmdq_pkt *pkt) +{ + struct cmdq_client *client = (struct cmdq_client *)pkt->cl; + + dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size, + DMA_TO_DEVICE); + kfree(pkt->va_base); + kfree(pkt); +} +EXPORT_SYMBOL(cmdq_pkt_destroy); + +static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code, + u32 arg_a, u32 arg_b) +{ + u64 *cmd_ptr; + + if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) { + /* + * In the case of allocated buffer size (pkt->buf_size) is used + * up, the real required size (pkt->cmdq_buf_size) is still + * increased, so that the user knows how much memory should be + * ultimately allocated after appending all commands and + * flushing the command packet. Therefor, the user can call + * cmdq_pkt_create() again with the real required buffer size. + */ + pkt->cmd_buf_size += CMDQ_INST_SIZE; + WARN_ONCE(1, "%s: buffer size %u is too small !\n", + __func__, (u32)pkt->buf_size); + return -ENOMEM; + } + cmd_ptr = pkt->va_base + pkt->cmd_buf_size; + (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b; + pkt->cmd_buf_size += CMDQ_INST_SIZE; + + return 0; +} + +int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset) +{ + u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) | + (subsys << CMDQ_SUBSYS_SHIFT); + + return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value); +} +EXPORT_SYMBOL(cmdq_pkt_write); + +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, + u32 subsys, u32 offset, u32 mask) +{ + u32 offset_mask = offset; + int err = 0; + + if (mask != 0xffffffff) { + err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask); + offset_mask |= CMDQ_WRITE_ENABLE_MASK; + } + err |= cmdq_pkt_write(pkt, value, subsys, offset_mask); + + return err; +} +EXPORT_SYMBOL(cmdq_pkt_write_mask); + +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event) +{ + u32 arg_b; + + if (event >= CMDQ_MAX_EVENT) + return -EINVAL; + + /* + * WFE arg_b + * bit 0-11: wait value + * bit 15: 1 - wait, 0 - no wait + * bit 16-27: update value + * bit 31: 1 - update, 0 - no update + */ + arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE; + + return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, arg_b); +} +EXPORT_SYMBOL(cmdq_pkt_wfe); + +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event) +{ + if (event >= CMDQ_MAX_EVENT) + return -EINVAL; + + return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, + CMDQ_WFE_UPDATE); +} +EXPORT_SYMBOL(cmdq_pkt_clear_event); + +static int cmdq_pkt_finalize(struct cmdq_pkt *pkt) +{ + int err; + + /* insert EOC and generate IRQ for each command iteration */ + err = cmdq_pkt_append_command(pkt, CMDQ_CODE_EOC, 0, CMDQ_EOC_IRQ_EN); + + /* JUMP to end */ + err |= cmdq_pkt_append_command(pkt, CMDQ_CODE_JUMP, 0, CMDQ_JUMP_PASS); + + return err; +} + +static void cmdq_pkt_flush_async_cb(struct cmdq_cb_data data) +{ + struct cmdq_pkt *pkt = (struct cmdq_pkt *)data.data; + struct cmdq_task_cb *cb = &pkt->cb; + struct cmdq_client *client = (struct cmdq_client *)pkt->cl; + + if (client->timeout_ms != CMDQ_NO_TIMEOUT) { + unsigned long flags = 0; + + spin_lock_irqsave(&client->lock, flags); + if (--client->pkt_cnt == 0) + del_timer(&client->timer); + else + mod_timer(&client->timer, jiffies + + msecs_to_jiffies(client->timeout_ms)); + spin_unlock_irqrestore(&client->lock, flags); + } + + dma_sync_single_for_cpu(client->chan->mbox->dev, pkt->pa_base, + pkt->cmd_buf_size, DMA_TO_DEVICE); + if (cb->cb) { + data.data = cb->data; + cb->cb(data); + } +} + +int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, + void *data) +{ + int err; + unsigned long flags = 0; + struct cmdq_client *client = (struct cmdq_client *)pkt->cl; + + err = cmdq_pkt_finalize(pkt); + if (err < 0) + return err; + + pkt->cb.cb = cb; + pkt->cb.data = data; + pkt->async_cb.cb = cmdq_pkt_flush_async_cb; + pkt->async_cb.data = pkt; + + dma_sync_single_for_device(client->chan->mbox->dev, pkt->pa_base, + pkt->cmd_buf_size, DMA_TO_DEVICE); + + if (client->timeout_ms != CMDQ_NO_TIMEOUT) { + spin_lock_irqsave(&client->lock, flags); + if (client->pkt_cnt++ == 0) + mod_timer(&client->timer, jiffies + + msecs_to_jiffies(client->timeout_ms)); + spin_unlock_irqrestore(&client->lock, flags); + } + + mbox_send_message(client->chan, pkt); + /* We can send next packet immediately, so just call txdone. */ + mbox_client_txdone(client->chan, 0); + + return 0; +} +EXPORT_SYMBOL(cmdq_pkt_flush_async); + +struct cmdq_flush_completion { + struct completion cmplt; + bool err; +}; + +static void cmdq_pkt_flush_cb(struct cmdq_cb_data data) +{ + struct cmdq_flush_completion *cmplt; + + cmplt = (struct cmdq_flush_completion *)data.data; + if (data.sta != CMDQ_CB_NORMAL) + cmplt->err = true; + else + cmplt->err = false; + complete(&cmplt->cmplt); +} + +int cmdq_pkt_flush(struct cmdq_pkt *pkt) +{ + struct cmdq_flush_completion cmplt; + int err; + + init_completion(&cmplt.cmplt); + err = cmdq_pkt_flush_async(pkt, cmdq_pkt_flush_cb, &cmplt); + if (err < 0) + return err; + wait_for_completion(&cmplt.cmplt); + + return cmplt.err ? -EFAULT : 0; +} +EXPORT_SYMBOL(cmdq_pkt_flush); + +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h new file mode 100644 index 000000000000..54ade13a9b15 --- /dev/null +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 MediaTek Inc. + * + */ + +#ifndef __MTK_CMDQ_H__ +#define __MTK_CMDQ_H__ + +#include +#include +#include + +#define CMDQ_NO_TIMEOUT 0xffffffffu + +/** cmdq event maximum */ +#define CMDQ_MAX_EVENT 0x3ff + +struct cmdq_pkt; + +struct cmdq_client { + spinlock_t lock; + u32 pkt_cnt; + struct mbox_client client; + struct mbox_chan *chan; + struct timer_list timer; + u32 timeout_ms; /* in unit of microsecond */ +}; + +/** + * cmdq_mbox_create() - create CMDQ mailbox client and channel + * @dev: device of CMDQ mailbox client + * @index: index of CMDQ mailbox channel + * @timeout: timeout of a pkt execution by GCE, in unit of microsecond, set + * CMDQ_NO_TIMEOUT if a timer is not used. + * + * Return: CMDQ mailbox client pointer + */ +struct cmdq_client *cmdq_mbox_create(struct device *dev, int index, + u32 timeout); + +/** + * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel + * @client: the CMDQ mailbox client + */ +void cmdq_mbox_destroy(struct cmdq_client *client); + +/** + * cmdq_pkt_create() - create a CMDQ packet + * @client: the CMDQ mailbox client + * @size: required CMDQ buffer size + * + * Return: CMDQ packet pointer + */ +struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size); + +/** + * cmdq_pkt_destroy() - destroy the CMDQ packet + * @pkt: the CMDQ packet + */ +void cmdq_pkt_destroy(struct cmdq_pkt *pkt); + +/** + * cmdq_pkt_write() - append write command to the CMDQ packet + * @pkt: the CMDQ packet + * @value: the specified target register value + * @subsys: the CMDQ sub system code + * @offset: register offset from CMDQ sub system + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset); + +/** + * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet + * @pkt: the CMDQ packet + * @value: the specified target register value + * @subsys: the CMDQ sub system code + * @offset: register offset from CMDQ sub system + * @mask: the specified target register mask + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, + u32 subsys, u32 offset, u32 mask); + +/** + * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet + * @pkt: the CMDQ packet + * @event: the desired event type to "wait and CLEAR" + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event); + +/** + * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet + * @pkt: the CMDQ packet + * @event: the desired event to be cleared + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event); + +/** + * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ + * packet and call back at the end of done packet + * @pkt: the CMDQ packet + * @cb: called at the end of done packet + * @data: this data will pass back to cb + * + * Return: 0 for success; else the error code is returned + * + * Trigger CMDQ to asynchronously execute the CMDQ packet and call back + * at the end of done packet. Note that this is an ASYNC function. When the + * function returned, it may or may not be finished. + */ +int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, + void *data); + +/** + * cmdq_pkt_flush() - trigger CMDQ to execute the CMDQ packet + * @pkt: the CMDQ packet + * + * Return: 0 for success; else the error code is returned + * + * Trigger CMDQ to execute the CMDQ packet. Note that this is a + * synchronous flush function. When the function returned, the recorded + * commands have been done. + */ +int cmdq_pkt_flush(struct cmdq_pkt *pkt); + +#endif /* __MTK_CMDQ_H__ */ -- cgit v1.2.3 From c2a70a319afb9e3dee16567cec4d9bf8dd358b59 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sun, 17 Jun 2018 19:02:15 +0200 Subject: dmaengine: pxa: make the filter function internal As the pxa architecture and all its related drivers do not rely anymore on the filter function, thanks to the slave map conversion, make pxad_filter_fn() static, and remove it from the global namespace. Signed-off-by: Robert Jarzmik Acked-by: Vinod Koul --- drivers/dma/pxa_dma.c | 5 ++--- include/linux/dma/pxa-dma.h | 11 ----------- 2 files changed, 2 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/drivers/dma/pxa_dma.c b/drivers/dma/pxa_dma.c index 825725057e00..c7a328f81485 100644 --- a/drivers/dma/pxa_dma.c +++ b/drivers/dma/pxa_dma.c @@ -179,7 +179,7 @@ static unsigned int pxad_drcmr(unsigned int line) return 0x1000 + line * 4; } -bool pxad_filter_fn(struct dma_chan *chan, void *param); +static bool pxad_filter_fn(struct dma_chan *chan, void *param); /* * Debug fs @@ -1500,7 +1500,7 @@ static struct platform_driver pxad_driver = { .remove = pxad_remove, }; -bool pxad_filter_fn(struct dma_chan *chan, void *param) +static bool pxad_filter_fn(struct dma_chan *chan, void *param) { struct pxad_chan *c = to_pxad_chan(chan); struct pxad_param *p = param; @@ -1513,7 +1513,6 @@ bool pxad_filter_fn(struct dma_chan *chan, void *param) return true; } -EXPORT_SYMBOL_GPL(pxad_filter_fn); module_platform_driver(pxad_driver); diff --git a/include/linux/dma/pxa-dma.h b/include/linux/dma/pxa-dma.h index 9fc594f69eff..fceb5df07097 100644 --- a/include/linux/dma/pxa-dma.h +++ b/include/linux/dma/pxa-dma.h @@ -23,15 +23,4 @@ struct pxad_param { enum pxad_chan_prio prio; }; -struct dma_chan; - -#ifdef CONFIG_PXA_DMA -bool pxad_filter_fn(struct dma_chan *chan, void *param); -#else -static inline bool pxad_filter_fn(struct dma_chan *chan, void *param) -{ - return false; -} -#endif - #endif /* _PXA_DMA_H_ */ -- cgit v1.2.3 From 685efffe37c921cf1d56dd3c8617dc67bc343a99 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 16 Nov 2018 16:49:27 +0100 Subject: soc: imx: gpcv2: add support for i.MX8MQ SoC The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/power/fsl,imx-gpcv2.txt | 7 +- drivers/soc/imx/Kconfig | 6 +- drivers/soc/imx/Makefile | 2 +- drivers/soc/imx/gpcv2.c | 208 ++++++++++++++++++++- include/dt-bindings/power/imx8mq-power.h | 21 +++ 5 files changed, 237 insertions(+), 7 deletions(-) create mode 100644 include/dt-bindings/power/imx8mq-power.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt index 9acce75b29ab..7c947a996df1 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt @@ -6,7 +6,9 @@ Control (PGC) for various power domains. Required properties: -- compatible: Should be "fsl,imx7d-gpc" +- compatible: Should be one of: + - "fsl,imx7d-gpc" + - "fsl,imx8mq-gpc" - reg: should be register base and length as documented in the datasheet @@ -22,7 +24,8 @@ which, in turn, is expected to contain the following: Required properties: - reg: Power domain index. Valid values are defined in - include/dt-bindings/power/imx7-power.h + include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and + include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc - #power-domain-cells: Should be 0 diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig index a5b86a28f343..2112d18dbb7b 100644 --- a/drivers/soc/imx/Kconfig +++ b/drivers/soc/imx/Kconfig @@ -1,8 +1,8 @@ menu "i.MX SoC drivers" -config IMX7_PM_DOMAINS - bool "i.MX7 PM domains" - depends on SOC_IMX7D || (COMPILE_TEST && OF) +config IMX_GPCV2_PM_DOMAINS + bool "i.MX GPCv2 PM domains" + depends on SOC_IMX7D || SOC_IMX8MQ || (COMPILE_TEST && OF) depends on PM select PM_GENERIC_DOMAINS default y if SOC_IMX7D diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index aab41a5cc317..506a6f3c2b9b 100644 --- a/drivers/soc/imx/Makefile +++ b/drivers/soc/imx/Makefile @@ -1,2 +1,2 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o -obj-$(CONFIG_IMX7_PM_DOMAINS) += gpcv2.o +obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index fe2cf6b61b05..8b4f48a2ca57 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -14,24 +14,55 @@ #include #include #include +#include #define GPC_LPCR_A_CORE_BSC 0x000 #define GPC_PGC_CPU_MAPPING 0x0ec + #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6) #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5) #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN BIT(4) #define IMX7_PCIE_PHY_A_CORE_DOMAIN BIT(3) #define IMX7_MIPI_PHY_A_CORE_DOMAIN BIT(2) +#define IMX8M_PCIE2_A53_DOMAIN BIT(15) +#define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14) +#define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13) +#define IMX8M_DISP_A53_DOMAIN BIT(12) +#define IMX8M_HDMI_A53_DOMAIN BIT(11) +#define IMX8M_VPU_A53_DOMAIN BIT(10) +#define IMX8M_GPU_A53_DOMAIN BIT(9) +#define IMX8M_DDR2_A53_DOMAIN BIT(8) +#define IMX8M_DDR1_A53_DOMAIN BIT(7) +#define IMX8M_OTG2_A53_DOMAIN BIT(5) +#define IMX8M_OTG1_A53_DOMAIN BIT(4) +#define IMX8M_PCIE1_A53_DOMAIN BIT(3) +#define IMX8M_MIPI_A53_DOMAIN BIT(2) + #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 #define GPC_PU_PGC_SW_PDN_REQ 0x104 + #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4) #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3) #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2) #define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1) #define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0) +#define IMX8M_PCIE2_SW_Pxx_REQ BIT(13) +#define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12) +#define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11) +#define IMX8M_DISP_SW_Pxx_REQ BIT(10) +#define IMX8M_HDMI_SW_Pxx_REQ BIT(9) +#define IMX8M_VPU_SW_Pxx_REQ BIT(8) +#define IMX8M_GPU_SW_Pxx_REQ BIT(7) +#define IMX8M_DDR2_SW_Pxx_REQ BIT(6) +#define IMX8M_DDR1_SW_Pxx_REQ BIT(5) +#define IMX8M_OTG2_SW_Pxx_REQ BIT(3) +#define IMX8M_OTG1_SW_Pxx_REQ BIT(2) +#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1) +#define IMX8M_MIPI_SW_Pxx_REQ BIT(0) + #define GPC_M4_PU_PDN_FLG 0x1bc /* @@ -43,6 +74,19 @@ #define IMX7_PGC_MIPI 16 #define IMX7_PGC_PCIE 17 #define IMX7_PGC_USB_HSIC 20 + +#define IMX8M_PGC_MIPI 16 +#define IMX8M_PGC_PCIE1 17 +#define IMX8M_PGC_OTG1 18 +#define IMX8M_PGC_OTG2 19 +#define IMX8M_PGC_DDR1 21 +#define IMX8M_PGC_GPU 23 +#define IMX8M_PGC_VPU 24 +#define IMX8M_PGC_DISP 26 +#define IMX8M_PGC_MIPI_CSI1 27 +#define IMX8M_PGC_MIPI_CSI2 28 +#define IMX8M_PGC_PCIE2 29 + #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) @@ -221,6 +265,167 @@ static const struct imx_pgc_domain_data imx7_pgc_domain_data = { .reg_access_table = &imx7_access_table, }; +static const struct imx_pgc_domain imx8m_pgc_domains[] = { + [IMX8M_POWER_DOMAIN_MIPI] = { + .genpd = { + .name = "mipi", + }, + .bits = { + .pxx = IMX8M_MIPI_SW_Pxx_REQ, + .map = IMX8M_MIPI_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_MIPI, + }, + + [IMX8M_POWER_DOMAIN_PCIE1] = { + .genpd = { + .name = "pcie1", + }, + .bits = { + .pxx = IMX8M_PCIE1_SW_Pxx_REQ, + .map = IMX8M_PCIE1_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_PCIE1, + }, + + [IMX8M_POWER_DOMAIN_USB_OTG1] = { + .genpd = { + .name = "usb-otg1", + }, + .bits = { + .pxx = IMX8M_OTG1_SW_Pxx_REQ, + .map = IMX8M_OTG1_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_OTG1, + }, + + [IMX8M_POWER_DOMAIN_USB_OTG2] = { + .genpd = { + .name = "usb-otg2", + }, + .bits = { + .pxx = IMX8M_OTG2_SW_Pxx_REQ, + .map = IMX8M_OTG2_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_OTG2, + }, + + [IMX8M_POWER_DOMAIN_DDR1] = { + .genpd = { + .name = "ddr1", + }, + .bits = { + .pxx = IMX8M_DDR1_SW_Pxx_REQ, + .map = IMX8M_DDR2_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_DDR1, + }, + + [IMX8M_POWER_DOMAIN_GPU] = { + .genpd = { + .name = "gpu", + }, + .bits = { + .pxx = IMX8M_GPU_SW_Pxx_REQ, + .map = IMX8M_GPU_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_GPU, + }, + + [IMX8M_POWER_DOMAIN_VPU] = { + .genpd = { + .name = "vpu", + }, + .bits = { + .pxx = IMX8M_VPU_SW_Pxx_REQ, + .map = IMX8M_VPU_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_VPU, + }, + + [IMX8M_POWER_DOMAIN_DISP] = { + .genpd = { + .name = "disp", + }, + .bits = { + .pxx = IMX8M_DISP_SW_Pxx_REQ, + .map = IMX8M_DISP_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_DISP, + }, + + [IMX8M_POWER_DOMAIN_MIPI_CSI1] = { + .genpd = { + .name = "mipi-csi1", + }, + .bits = { + .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ, + .map = IMX8M_MIPI_CSI1_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_MIPI_CSI1, + }, + + [IMX8M_POWER_DOMAIN_MIPI_CSI2] = { + .genpd = { + .name = "mipi-csi2", + }, + .bits = { + .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ, + .map = IMX8M_MIPI_CSI2_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_MIPI_CSI2, + }, + + [IMX8M_POWER_DOMAIN_PCIE2] = { + .genpd = { + .name = "pcie2", + }, + .bits = { + .pxx = IMX8M_PCIE2_SW_Pxx_REQ, + .map = IMX8M_PCIE2_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_PCIE2, + }, +}; + +static const struct regmap_range imx8m_yes_ranges[] = { + regmap_reg_range(GPC_LPCR_A_CORE_BSC, + GPC_M4_PU_PDN_FLG), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI), + GPC_PGC_SR(IMX8M_PGC_MIPI)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1), + GPC_PGC_SR(IMX8M_PGC_PCIE1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1), + GPC_PGC_SR(IMX8M_PGC_OTG1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2), + GPC_PGC_SR(IMX8M_PGC_OTG2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1), + GPC_PGC_SR(IMX8M_PGC_DDR1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU), + GPC_PGC_SR(IMX8M_PGC_GPU)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU), + GPC_PGC_SR(IMX8M_PGC_VPU)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP), + GPC_PGC_SR(IMX8M_PGC_DISP)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1), + GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2), + GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2), + GPC_PGC_SR(IMX8M_PGC_PCIE2)), +}; + +static const struct regmap_access_table imx8m_access_table = { + .yes_ranges = imx8m_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(imx8m_yes_ranges), +}; + +static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { + .domains = imx8m_pgc_domains, + .domains_num = ARRAY_SIZE(imx8m_pgc_domains), + .reg_access_table = &imx8m_access_table, +}; + static int imx_pgc_domain_probe(struct platform_device *pdev) { struct imx_pgc_domain *domain = pdev->dev.platform_data; @@ -235,7 +440,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) dev_err(domain->dev, "Failed to get domain's regulator\n"); return PTR_ERR(domain->regulator); } - } else { + } else if (domain->voltage) { regulator_set_voltage(domain->regulator, domain->voltage, domain->voltage); } @@ -376,6 +581,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) static const struct of_device_id imx_gpcv2_dt_ids[] = { { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, }, + { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, }, { } }; diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h new file mode 100644 index 000000000000..8a513bd9166e --- /dev/null +++ b/include/dt-bindings/power/imx8mq-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2018 Pengutronix, Lucas Stach + */ + +#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__ +#define __DT_BINDINGS_IMX8MQ_POWER_H__ + +#define IMX8M_POWER_DOMAIN_MIPI 0 +#define IMX8M_POWER_DOMAIN_PCIE1 1 +#define IMX8M_POWER_DOMAIN_USB_OTG1 2 +#define IMX8M_POWER_DOMAIN_USB_OTG2 3 +#define IMX8M_POWER_DOMAIN_DDR1 4 +#define IMX8M_POWER_DOMAIN_GPU 5 +#define IMX8M_POWER_DOMAIN_VPU 6 +#define IMX8M_POWER_DOMAIN_DISP 7 +#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8 +#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 +#define IMX8M_POWER_DOMAIN_PCIE2 10 + +#endif -- cgit v1.2.3 From 16ad9501b1f2edebe24f8cf3c09da0695871986b Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Wed, 21 Nov 2018 21:32:25 -0500 Subject: firmware: qcom: scm: fix compilation error when disabled This fixes the case when CONFIG_QCOM_SCM is not enabled, and linux/errno.h has not been included previously. Signed-off-by: Jonathan Marek Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- include/linux/qcom_scm.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 06996ad4f2bc..1637385bcc17 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -67,6 +67,9 @@ extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); #else + +#include + static inline int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) { -- cgit v1.2.3 From fee10bd2267868f2a3e7ba008ef7665aac5e4412 Mon Sep 17 00:00:00 2001 From: Naga Sureshkumar Relli Date: Thu, 6 Dec 2018 18:17:34 +0530 Subject: memory: pl353: Add driver for arm pl353 static memory controller Add driver for arm pl353 static memory controller. This controller is used in Xilinx Zynq SoC for interfacing the NAND and NOR/SRAM memory devices. Signed-off-by: Naga Sureshkumar Relli Reviewed-by: Linus Walleij Signed-off-by: Michal Simek --- drivers/memory/Kconfig | 9 + drivers/memory/Makefile | 1 + drivers/memory/pl353-smc.c | 463 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/pl353-smc.h | 30 +++ 4 files changed, 503 insertions(+) create mode 100644 drivers/memory/pl353-smc.c create mode 100644 include/linux/pl353-smc.h (limited to 'include') diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 63389f075f1d..2d91b00e3591 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -145,6 +145,15 @@ config DA8XX_DDRCTL Texas Instruments da8xx SoCs. It's used to tweak various memory controller configuration options. +config PL353_SMC + tristate "ARM PL35X Static Memory Controller(SMC) driver" + default y + depends on ARM + depends on ARM_AMBA + help + This driver is for the ARM PL351/PL353 Static Memory + Controller(SMC) module. + source "drivers/memory/samsung/Kconfig" source "drivers/memory/tegra/Kconfig" diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index a01ab3e22f94..90161dec6fa5 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o obj-$(CONFIG_MTK_SMI) += mtk-smi.o obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o +obj-$(CONFIG_PL353_SMC) += pl353-smc.o obj-$(CONFIG_SAMSUNG_MC) += samsung/ obj-$(CONFIG_TEGRA_MC) += tegra/ diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c new file mode 100644 index 000000000000..73bd3023202f --- /dev/null +++ b/drivers/memory/pl353-smc.c @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM PL353 SMC driver + * + * Copyright (C) 2012 - 2018 Xilinx, Inc + * Author: Punnaiah Choudary Kalluri + * Author: Naga Sureshkumar Relli + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register definitions */ +#define PL353_SMC_MEMC_STATUS_OFFS 0 /* Controller status reg, RO */ +#define PL353_SMC_CFG_CLR_OFFS 0xC /* Clear config reg, WO */ +#define PL353_SMC_DIRECT_CMD_OFFS 0x10 /* Direct command reg, WO */ +#define PL353_SMC_SET_CYCLES_OFFS 0x14 /* Set cycles register, WO */ +#define PL353_SMC_SET_OPMODE_OFFS 0x18 /* Set opmode register, WO */ +#define PL353_SMC_ECC_STATUS_OFFS 0x400 /* ECC status register */ +#define PL353_SMC_ECC_MEMCFG_OFFS 0x404 /* ECC mem config reg */ +#define PL353_SMC_ECC_MEMCMD1_OFFS 0x408 /* ECC mem cmd1 reg */ +#define PL353_SMC_ECC_MEMCMD2_OFFS 0x40C /* ECC mem cmd2 reg */ +#define PL353_SMC_ECC_VALUE0_OFFS 0x418 /* ECC value 0 reg */ + +/* Controller status register specific constants */ +#define PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT 6 + +/* Clear configuration register specific constants */ +#define PL353_SMC_CFG_CLR_INT_CLR_1 0x10 +#define PL353_SMC_CFG_CLR_ECC_INT_DIS_1 0x40 +#define PL353_SMC_CFG_CLR_INT_DIS_1 0x2 +#define PL353_SMC_CFG_CLR_DEFAULT_MASK (PL353_SMC_CFG_CLR_INT_CLR_1 | \ + PL353_SMC_CFG_CLR_ECC_INT_DIS_1 | \ + PL353_SMC_CFG_CLR_INT_DIS_1) + +/* Set cycles register specific constants */ +#define PL353_SMC_SET_CYCLES_T0_MASK 0xF +#define PL353_SMC_SET_CYCLES_T0_SHIFT 0 +#define PL353_SMC_SET_CYCLES_T1_MASK 0xF +#define PL353_SMC_SET_CYCLES_T1_SHIFT 4 +#define PL353_SMC_SET_CYCLES_T2_MASK 0x7 +#define PL353_SMC_SET_CYCLES_T2_SHIFT 8 +#define PL353_SMC_SET_CYCLES_T3_MASK 0x7 +#define PL353_SMC_SET_CYCLES_T3_SHIFT 11 +#define PL353_SMC_SET_CYCLES_T4_MASK 0x7 +#define PL353_SMC_SET_CYCLES_T4_SHIFT 14 +#define PL353_SMC_SET_CYCLES_T5_MASK 0x7 +#define PL353_SMC_SET_CYCLES_T5_SHIFT 17 +#define PL353_SMC_SET_CYCLES_T6_MASK 0xF +#define PL353_SMC_SET_CYCLES_T6_SHIFT 20 + +/* ECC status register specific constants */ +#define PL353_SMC_ECC_STATUS_BUSY BIT(6) +#define PL353_SMC_ECC_REG_SIZE_OFFS 4 + +/* ECC memory config register specific constants */ +#define PL353_SMC_ECC_MEMCFG_MODE_MASK 0xC +#define PL353_SMC_ECC_MEMCFG_MODE_SHIFT 2 +#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK 0xC + +#define PL353_SMC_DC_UPT_NAND_REGS ((4 << 23) | /* CS: NAND chip */ \ + (2 << 21)) /* UpdateRegs operation */ + +#define PL353_NAND_ECC_CMD1 ((0x80) | /* Write command */ \ + (0 << 8) | /* Read command */ \ + (0x30 << 16) | /* Read End command */ \ + (1 << 24)) /* Read End command calid */ + +#define PL353_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \ + (5 << 8) | /* Read col change cmd */ \ + (0xE0 << 16) | /* Read col change end cmd */ \ + (1 << 24)) /* Read col change end cmd valid */ +#define PL353_NAND_ECC_BUSY_TIMEOUT (1 * HZ) +/** + * struct pl353_smc_data - Private smc driver structure + * @memclk: Pointer to the peripheral clock + * @aclk: Pointer to the APER clock + */ +struct pl353_smc_data { + struct clk *memclk; + struct clk *aclk; +}; + +/* SMC virtual register base */ +static void __iomem *pl353_smc_base; + +/** + * pl353_smc_set_buswidth - Set memory buswidth + * @bw: Memory buswidth (8 | 16) + * Return: 0 on success or negative errno. + */ +int pl353_smc_set_buswidth(unsigned int bw) +{ + if (bw != PL353_SMC_MEM_WIDTH_8 && bw != PL353_SMC_MEM_WIDTH_16) + return -EINVAL; + + writel(bw, pl353_smc_base + PL353_SMC_SET_OPMODE_OFFS); + writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base + + PL353_SMC_DIRECT_CMD_OFFS); + + return 0; +} +EXPORT_SYMBOL_GPL(pl353_smc_set_buswidth); + +/** + * pl353_smc_set_cycles - Set memory timing parameters + * @timings: NAND controller timing parameters + * + * Sets NAND chip specific timing parameters. + */ +void pl353_smc_set_cycles(u32 timings[]) +{ + /* + * Set write pulse timing. This one is easy to extract: + * + * NWE_PULSE = tWP + */ + timings[0] &= PL353_SMC_SET_CYCLES_T0_MASK; + timings[1] = (timings[1] & PL353_SMC_SET_CYCLES_T1_MASK) << + PL353_SMC_SET_CYCLES_T1_SHIFT; + timings[2] = (timings[2] & PL353_SMC_SET_CYCLES_T2_MASK) << + PL353_SMC_SET_CYCLES_T2_SHIFT; + timings[3] = (timings[3] & PL353_SMC_SET_CYCLES_T3_MASK) << + PL353_SMC_SET_CYCLES_T3_SHIFT; + timings[4] = (timings[4] & PL353_SMC_SET_CYCLES_T4_MASK) << + PL353_SMC_SET_CYCLES_T4_SHIFT; + timings[5] = (timings[5] & PL353_SMC_SET_CYCLES_T5_MASK) << + PL353_SMC_SET_CYCLES_T5_SHIFT; + timings[6] = (timings[6] & PL353_SMC_SET_CYCLES_T6_MASK) << + PL353_SMC_SET_CYCLES_T6_SHIFT; + timings[0] |= timings[1] | timings[2] | timings[3] | + timings[4] | timings[5] | timings[6]; + + writel(timings[0], pl353_smc_base + PL353_SMC_SET_CYCLES_OFFS); + writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base + + PL353_SMC_DIRECT_CMD_OFFS); +} +EXPORT_SYMBOL_GPL(pl353_smc_set_cycles); + +/** + * pl353_smc_ecc_is_busy - Read ecc busy flag + * Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle + */ +bool pl353_smc_ecc_is_busy(void) +{ + return ((readl(pl353_smc_base + PL353_SMC_ECC_STATUS_OFFS) & + PL353_SMC_ECC_STATUS_BUSY) == PL353_SMC_ECC_STATUS_BUSY); +} +EXPORT_SYMBOL_GPL(pl353_smc_ecc_is_busy); + +/** + * pl353_smc_get_ecc_val - Read ecc_valueN registers + * @ecc_reg: Index of the ecc_value reg (0..3) + * Return: the content of the requested ecc_value register. + * + * There are four valid ecc_value registers. The argument is truncated to stay + * within this valid boundary. + */ +u32 pl353_smc_get_ecc_val(int ecc_reg) +{ + u32 addr, reg; + + addr = PL353_SMC_ECC_VALUE0_OFFS + + (ecc_reg * PL353_SMC_ECC_REG_SIZE_OFFS); + reg = readl(pl353_smc_base + addr); + + return reg; +} +EXPORT_SYMBOL_GPL(pl353_smc_get_ecc_val); + +/** + * pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit + * Return: the raw_int_status1 bit from the memc_status register + */ +int pl353_smc_get_nand_int_status_raw(void) +{ + u32 reg; + + reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS); + reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT; + reg &= 1; + + return reg; +} +EXPORT_SYMBOL_GPL(pl353_smc_get_nand_int_status_raw); + +/** + * pl353_smc_clr_nand_int - Clear NAND interrupt + */ +void pl353_smc_clr_nand_int(void) +{ + writel(PL353_SMC_CFG_CLR_INT_CLR_1, + pl353_smc_base + PL353_SMC_CFG_CLR_OFFS); +} +EXPORT_SYMBOL_GPL(pl353_smc_clr_nand_int); + +/** + * pl353_smc_set_ecc_mode - Set SMC ECC mode + * @mode: ECC mode (BYPASS, APB, MEM) + * Return: 0 on success or negative errno. + */ +int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode) +{ + u32 reg; + int ret = 0; + + switch (mode) { + case PL353_SMC_ECCMODE_BYPASS: + case PL353_SMC_ECCMODE_APB: + case PL353_SMC_ECCMODE_MEM: + + reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); + reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK; + reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT; + writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); + + break; + default: + ret = -EINVAL; + } + + return ret; +} +EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_mode); + +/** + * pl353_smc_set_ecc_pg_size - Set SMC ECC page size + * @pg_sz: ECC page size + * Return: 0 on success or negative errno. + */ +int pl353_smc_set_ecc_pg_size(unsigned int pg_sz) +{ + u32 reg, sz; + + switch (pg_sz) { + case 0: + sz = 0; + break; + case SZ_512: + sz = 1; + break; + case SZ_1K: + sz = 2; + break; + case SZ_2K: + sz = 3; + break; + default: + return -EINVAL; + } + + reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); + reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK; + reg |= sz; + writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); + + return 0; +} +EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_pg_size); + +static int __maybe_unused pl353_smc_suspend(struct device *dev) +{ + struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev); + + clk_disable(pl353_smc->memclk); + clk_disable(pl353_smc->aclk); + + return 0; +} + +static int __maybe_unused pl353_smc_resume(struct device *dev) +{ + int ret; + struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev); + + ret = clk_enable(pl353_smc->aclk); + if (ret) { + dev_err(dev, "Cannot enable axi domain clock.\n"); + return ret; + } + + ret = clk_enable(pl353_smc->memclk); + if (ret) { + dev_err(dev, "Cannot enable memory clock.\n"); + clk_disable(pl353_smc->aclk); + return ret; + } + + return ret; +} + +static struct amba_driver pl353_smc_driver; + +static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend, + pl353_smc_resume); + +/** + * pl353_smc_init_nand_interface - Initialize the NAND interface + * @adev: Pointer to the amba_device struct + * @nand_node: Pointer to the pl353_nand device_node struct + */ +static void pl353_smc_init_nand_interface(struct amba_device *adev, + struct device_node *nand_node) +{ + unsigned long timeout; + + pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_8); + writel(PL353_SMC_CFG_CLR_INT_CLR_1, + pl353_smc_base + PL353_SMC_CFG_CLR_OFFS); + writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base + + PL353_SMC_DIRECT_CMD_OFFS); + + timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT; + /* Wait till the ECC operation is complete */ + do { + if (pl353_smc_ecc_is_busy()) + cpu_relax(); + else + break; + } while (!time_after_eq(jiffies, timeout)); + + if (time_after_eq(jiffies, timeout)) + return; + + writel(PL353_NAND_ECC_CMD1, + pl353_smc_base + PL353_SMC_ECC_MEMCMD1_OFFS); + writel(PL353_NAND_ECC_CMD2, + pl353_smc_base + PL353_SMC_ECC_MEMCMD2_OFFS); +} + +static const struct of_device_id pl353_smc_supported_children[] = { + { + .compatible = "cfi-flash" + }, + { + .compatible = "arm,pl353-nand-r2p1", + .data = pl353_smc_init_nand_interface + }, + {} +}; + +static int pl353_smc_probe(struct amba_device *adev, const struct amba_id *id) +{ + struct pl353_smc_data *pl353_smc; + struct device_node *child; + struct resource *res; + int err; + struct device_node *of_node = adev->dev.of_node; + static void (*init)(struct amba_device *adev, + struct device_node *nand_node); + const struct of_device_id *match = NULL; + + pl353_smc = devm_kzalloc(&adev->dev, sizeof(*pl353_smc), GFP_KERNEL); + if (!pl353_smc) + return -ENOMEM; + + /* Get the NAND controller virtual address */ + res = &adev->res; + pl353_smc_base = devm_ioremap_resource(&adev->dev, res); + if (IS_ERR(pl353_smc_base)) + return PTR_ERR(pl353_smc_base); + + pl353_smc->aclk = devm_clk_get(&adev->dev, "apb_pclk"); + if (IS_ERR(pl353_smc->aclk)) { + dev_err(&adev->dev, "aclk clock not found.\n"); + return PTR_ERR(pl353_smc->aclk); + } + + pl353_smc->memclk = devm_clk_get(&adev->dev, "memclk"); + if (IS_ERR(pl353_smc->memclk)) { + dev_err(&adev->dev, "memclk clock not found.\n"); + return PTR_ERR(pl353_smc->memclk); + } + + err = clk_prepare_enable(pl353_smc->aclk); + if (err) { + dev_err(&adev->dev, "Unable to enable AXI clock.\n"); + return err; + } + + err = clk_prepare_enable(pl353_smc->memclk); + if (err) { + dev_err(&adev->dev, "Unable to enable memory clock.\n"); + goto out_clk_dis_aper; + } + + amba_set_drvdata(adev, pl353_smc); + + /* clear interrupts */ + writel(PL353_SMC_CFG_CLR_DEFAULT_MASK, + pl353_smc_base + PL353_SMC_CFG_CLR_OFFS); + + /* Find compatible children. Only a single child is supported */ + for_each_available_child_of_node(of_node, child) { + match = of_match_node(pl353_smc_supported_children, child); + if (!match) { + dev_warn(&adev->dev, "unsupported child node\n"); + continue; + } + break; + } + if (!match) { + dev_err(&adev->dev, "no matching children\n"); + goto out_clk_disable; + } + + init = match->data; + if (init) + init(adev, child); + of_platform_device_create(child, NULL, &adev->dev); + + return 0; + +out_clk_disable: + clk_disable_unprepare(pl353_smc->memclk); +out_clk_dis_aper: + clk_disable_unprepare(pl353_smc->aclk); + + return err; +} + +static int pl353_smc_remove(struct amba_device *adev) +{ + struct pl353_smc_data *pl353_smc = amba_get_drvdata(adev); + + clk_disable_unprepare(pl353_smc->memclk); + clk_disable_unprepare(pl353_smc->aclk); + + return 0; +} + +static const struct amba_id pl353_ids[] = { + { + .id = 0x00041353, + .mask = 0x000fffff, + }, + { 0, 0 }, +}; +MODULE_DEVICE_TABLE(amba, pl353_ids); + +static struct amba_driver pl353_smc_driver = { + .drv = { + .owner = THIS_MODULE, + .name = "pl353-smc", + .pm = &pl353_smc_dev_pm_ops, + }, + .id_table = pl353_ids, + .probe = pl353_smc_probe, + .remove = pl353_smc_remove, +}; + +module_amba_driver(pl353_smc_driver); + +MODULE_AUTHOR("Xilinx, Inc."); +MODULE_DESCRIPTION("ARM PL353 SMC Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/pl353-smc.h b/include/linux/pl353-smc.h new file mode 100644 index 000000000000..0e0d3df9bf72 --- /dev/null +++ b/include/linux/pl353-smc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ARM PL353 SMC Driver Header + * + * Copyright (C) 2012 - 2018 Xilinx, Inc + */ + +#ifndef __LINUX_PL353_SMC_H +#define __LINUX_PL353_SMC_H + +enum pl353_smc_ecc_mode { + PL353_SMC_ECCMODE_BYPASS = 0, + PL353_SMC_ECCMODE_APB = 1, + PL353_SMC_ECCMODE_MEM = 2 +}; + +enum pl353_smc_mem_width { + PL353_SMC_MEM_WIDTH_8 = 0, + PL353_SMC_MEM_WIDTH_16 = 1 +}; + +u32 pl353_smc_get_ecc_val(int ecc_reg); +bool pl353_smc_ecc_is_busy(void); +int pl353_smc_get_nand_int_status_raw(void); +void pl353_smc_clr_nand_int(void); +int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode); +int pl353_smc_set_ecc_pg_size(unsigned int pg_sz); +int pl353_smc_set_buswidth(unsigned int bw); +void pl353_smc_set_cycles(u32 timings[]); +#endif -- cgit v1.2.3