From 05308d7e7bbc932025f1dafc401c73ce83c6f414 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 24 Jun 2019 17:06:13 +0200 Subject: clk: tegra: Reimplement SOR clocks on Tegra210 In order to allow the display driver to deal uniformly with all SOR generations, implement the SOR clocks in a way that is compatible with Tegra186 and later. Acked-by: Stephen Boyd Signed-off-by: Thierry Reding --- include/dt-bindings/clock/tegra210-car.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 80590c2a117e..44f60623f99b 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -308,7 +308,8 @@ #define TEGRA210_CLK_CLK_OUT_2 278 #define TEGRA210_CLK_CLK_OUT_3 279 #define TEGRA210_CLK_BLINK 280 -/* 281 */ +#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ +#define TEGRA210_CLK_SOR0_OUT 281 #define TEGRA210_CLK_SOR1_OUT 282 /* 283 */ #define TEGRA210_CLK_XUSB_HOST_SRC 284 @@ -390,8 +391,7 @@ #define TEGRA210_CLK_CLK_OUT_3_MUX 358 #define TEGRA210_CLK_DSIA_MUX 359 #define TEGRA210_CLK_DSIB_MUX 360 -#define TEGRA210_CLK_SOR0_LVDS 361 /* deprecated */ -#define TEGRA210_CLK_SOR0_OUT 361 +/* 361 */ #define TEGRA210_CLK_XUSB_SS_DIV2 362 #define TEGRA210_CLK_PLL_M_UD 363 -- cgit v1.2.3