// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree file for the AM62P main domain peripherals
 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_main {
	oc_sram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x00 0x70000000 0x00 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x70000000 0x10000>;
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
		/*
		 * vcpumntirq:
		 * virtual CPU interface maintenance interrupt
		 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	dmss: bus@48000000 {
		bootph-all;
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		dma-ranges;
		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;

		ti,sci-dev-id = <25>;

		secure_proxy_main: mailbox@4d000000 {
			bootph-all;
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x4d000000 0x00 0x80000>,
			      <0x00 0x4a600000 0x00 0x80000>,
			      <0x00 0x4a400000 0x00 0x80000>;
			interrupt-names = "rx_012";
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	dmsc: system-controller@44043000 {
		bootph-all;
		compatible = "ti,k2g-sci";
		ti,host-id = <12>;
		mbox-names = "rx", "tx";
		mboxes = <&secure_proxy_main 12>,
			 <&secure_proxy_main 13>;
		reg-names = "debug_messages";
		reg = <0x00 0x44043000 0x00 0xfe0>;

		k3_pds: power-controller {
			bootph-all;
			compatible = "ti,sci-pm-domain";
			#power-domain-cells = <2>;
		};

		k3_clks: clock-controller {
			bootph-all;
			compatible = "ti,k2g-sci-clk";
			#clock-cells = <2>;
		};

		k3_reset: reset-controller {
			bootph-all;
			compatible = "ti,sci-reset";
			#reset-cells = <2>;
		};
	};

	main_pmx0: pinctrl@f4000 {
		bootph-all;
		compatible = "pinctrl-single";
		reg = <0x00 0xf4000 0x00 0x2ac>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	main_timer0: timer@2400000 {
		bootph-all;
		compatible = "ti,am654-timer";
		reg = <0x00 0x2400000 0x00 0x400>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 36 2>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 36 2>;
		assigned-clock-parents = <&k3_clks 36 3>;
		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_uart0: serial@2800000 {
		compatible = "ti,am64-uart", "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x100>;
		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 146 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	main_uart1: serial@2810000 {
		compatible = "ti,am64-uart", "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x100>;
		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 152 0>;
		clock-names = "fclk";
		status = "disabled";
	};
};