/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef _XE_REGS_H_ #define _XE_REGS_H_ #include "regs/xe_reg_defs.h" #define RENDER_RING_BASE 0x02000 #define BSD_RING_BASE 0x1c0000 #define BSD2_RING_BASE 0x1c4000 #define BSD3_RING_BASE 0x1d0000 #define BSD4_RING_BASE 0x1d4000 #define XEHP_BSD5_RING_BASE 0x1e0000 #define XEHP_BSD6_RING_BASE 0x1e4000 #define XEHP_BSD7_RING_BASE 0x1f0000 #define XEHP_BSD8_RING_BASE 0x1f4000 #define VEBOX_RING_BASE 0x1c8000 #define VEBOX2_RING_BASE 0x1d8000 #define XEHP_VEBOX3_RING_BASE 0x1e8000 #define XEHP_VEBOX4_RING_BASE 0x1f8000 #define COMPUTE0_RING_BASE 0x1a000 #define COMPUTE1_RING_BASE 0x1c000 #define COMPUTE2_RING_BASE 0x1e000 #define COMPUTE3_RING_BASE 0x26000 #define BLT_RING_BASE 0x22000 #define XEHPC_BCS1_RING_BASE 0x3e0000 #define XEHPC_BCS2_RING_BASE 0x3e2000 #define XEHPC_BCS3_RING_BASE 0x3e4000 #define XEHPC_BCS4_RING_BASE 0x3e6000 #define XEHPC_BCS5_RING_BASE 0x3e8000 #define XEHPC_BCS6_RING_BASE 0x3ea000 #define XEHPC_BCS7_RING_BASE 0x3ec000 #define XEHPC_BCS8_RING_BASE 0x3ee000 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4) #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) #define GT_RENDER_USER_INTERRUPT REG_BIT(0) #define FF_THREAD_MODE XE_REG(0x20a0) #define FF_TESSELATION_DOP_GATE_DISABLE BIT(19) #define TIMESTAMP_OVERRIDE XE_REG(0x44074) #define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12) #define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0) #define PCU_IRQ_OFFSET 0x444e0 #define GU_MISC_IRQ_OFFSET 0x444f0 #define GU_MISC_GSE REG_BIT(27) #define TRANSCODER_A_OFFSET 0x60000 #define TRANSCODER_B_OFFSET 0x61000 #define TRANSCODER_C_OFFSET 0x62000 #define TRANSCODER_D_OFFSET 0x63000 #define TRANSCODER_DSI0_OFFSET 0x6b000 #define TRANSCODER_DSI1_OFFSET 0x6b800 #define PIPE_A_OFFSET 0x70000 #define PIPE_B_OFFSET 0x71000 #define PIPE_C_OFFSET 0x72000 #define PIPE_D_OFFSET 0x73000 #define PIPE_DSI0_OFFSET 0x7b000 #define PIPE_DSI1_OFFSET 0x7b800 #define SOFTWARE_FLAGS_SPR33 XE_REG(0x4f084) #define GU_CNTL XE_REG(0x101010) #define LMEM_INIT REG_BIT(7) #define GGC XE_REG(0x108040) #define GMS_MASK REG_GENMASK(15, 8) #define GGMS_MASK REG_GENMASK(7, 6) #define DSMBASE XE_REG(0x1080C0) #define BDSM_MASK REG_GENMASK64(63, 20) #define GSMBASE XE_REG(0x108100) #define STOLEN_RESERVED XE_REG(0x1082c0) #define WOPCM_SIZE_MASK REG_GENMASK64(8, 7) #define MTL_RP_STATE_CAP XE_REG(0x138000) #define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c) #define MTL_MEDIAP_STATE_CAP XE_REG(0x138020) #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) #define MTL_MPE_FREQUENCY XE_REG(0x13802c) #define MTL_RPE_MASK REG_GENMASK(8, 0) #define DG1_MSTR_TILE_INTR XE_REG(0x190008) #define DG1_MSTR_IRQ REG_BIT(31) #define DG1_MSTR_TILE(t) REG_BIT(t) #define GFX_MSTR_IRQ XE_REG(0x190010) #define MASTER_IRQ REG_BIT(31) #define GU_MISC_IRQ REG_BIT(29) #define DISPLAY_IRQ REG_BIT(16) #define GT_DW_IRQ(x) REG_BIT(x) #define PVC_RP_STATE_CAP XE_REG(0x281014) #endif