1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
|
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car V3U (R8A779A0) SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a779a0-sysc.h>
/ {
compatible = "renesas,r8a779a0";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
a76_0: cpu@0 {
compatible = "arm,cortex-a76";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA76_0>;
};
L3_CA76_0: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A779A0_PD_A2E0D0>;
cache-unified;
cache-level = <3>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
pmu_a76 {
compatible = "arm,cortex-a76-pmu";
interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a779a0-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 907>;
status = "disabled";
};
pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-r8a779a0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
<0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
<0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
};
gpio0: gpio@e6058180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6058180 0 0x54>;
interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 916>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 0 28>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@e6050180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6050180 0 0x54>;
interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 32 31>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@e6050980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6050980 0 0x54>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 64 25>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@e6058980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6058980 0 0x54>;
interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 916>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 96 17>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@e6060180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6060180 0 0x54>;
interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 128 27>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@e6060980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6060980 0 0x54>;
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 160 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@e6068180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6068180 0 0x54>;
interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 918>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 192 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio@e6068980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6068980 0 0x54>;
interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 918>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 224 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio8: gpio@e6069180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6069180 0 0x54>;
interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 918>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 256 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio9: gpio@e6069980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6069980 0 0x54>;
interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 918>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 288 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779a0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a779a0-rst";
reg = <0 0xe6160000 0 0x4000>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a779a0-sysc";
reg = <0 0xe6180000 0 0x4000>;
#power-domain-cells = <1>;
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};
|