summaryrefslogtreecommitdiff
path: root/arch/mips/loongson64/cpucfg-emul.c
blob: cd619b47ba1f63ff410e01017c9043695970acaf (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
// SPDX-License-Identifier: GPL-2.0

#include <linux/smp.h>
#include <linux/types.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/elf.h>

#include <loongson_regs.h>
#include <cpucfg-emul.h>

static bool is_loongson(struct cpuinfo_mips *c)
{
	switch (c->processor_id & PRID_COMP_MASK) {
	case PRID_COMP_LEGACY:
		return ((c->processor_id & PRID_IMP_MASK) ==
			PRID_IMP_LOONGSON_64C);

	case PRID_COMP_LOONGSON:
		return true;

	default:
		return false;
	}
}

static u32 get_loongson_fprev(struct cpuinfo_mips *c)
{
	return c->fpu_id & LOONGSON_FPREV_MASK;
}

static bool cpu_has_uca(void)
{
	u32 diag = read_c0_diag();
	u32 new_diag;

	if (diag & LOONGSON_DIAG_UCAC)
		/* UCA is already enabled. */
		return true;

	/* See if UCAC bit can be flipped on. This should be safe. */
	new_diag = diag | LOONGSON_DIAG_UCAC;
	write_c0_diag(new_diag);
	new_diag = read_c0_diag();
	write_c0_diag(diag);

	return (new_diag & LOONGSON_DIAG_UCAC) != 0;
}

static void probe_uca(struct cpuinfo_mips *c)
{
	if (cpu_has_uca())
		c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LSUCA;
}

static void decode_loongson_config6(struct cpuinfo_mips *c)
{
	u32 config6 = read_c0_config6();

	if (config6 & MIPS_CONF6_LOONGSON_SFBEN)
		c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP;
	if (config6 & MIPS_CONF6_LOONGSON_LLEXC)
		c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC;
	if (config6 & MIPS_CONF6_LOONGSON_SCRAND)
		c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND;
}

static void patch_cpucfg_sel1(struct cpuinfo_mips *c)
{
	u64 ases = c->ases;
	u64 options = c->options;
	u32 data = c->loongson3_cpucfg_data[0];

	if (options & MIPS_CPU_FPU) {
		data |= LOONGSON_CFG1_FP;
		data |= get_loongson_fprev(c) << LOONGSON_CFG1_FPREV_OFFSET;
	}
	if (ases & MIPS_ASE_LOONGSON_MMI)
		data |= LOONGSON_CFG1_MMI;
	if (ases & MIPS_ASE_MSA)
		data |= LOONGSON_CFG1_MSA1;

	c->loongson3_cpucfg_data[0] = data;
}

static void patch_cpucfg_sel2(struct cpuinfo_mips *c)
{
	u64 ases = c->ases;
	u64 options = c->options;
	u32 data = c->loongson3_cpucfg_data[1];

	if (ases & MIPS_ASE_LOONGSON_EXT)
		data |= LOONGSON_CFG2_LEXT1;
	if (ases & MIPS_ASE_LOONGSON_EXT2)
		data |= LOONGSON_CFG2_LEXT2;
	if (options & MIPS_CPU_LDPTE)
		data |= LOONGSON_CFG2_LSPW;

	if (ases & MIPS_ASE_VZ)
		data |= LOONGSON_CFG2_LVZP;
	else
		data &= ~LOONGSON_CFG2_LVZREV;

	c->loongson3_cpucfg_data[1] = data;
}

static void patch_cpucfg_sel3(struct cpuinfo_mips *c)
{
	u64 ases = c->ases;
	u32 data = c->loongson3_cpucfg_data[2];

	if (ases & MIPS_ASE_LOONGSON_CAM) {
		data |= LOONGSON_CFG3_LCAMP;
	} else {
		data &= ~LOONGSON_CFG3_LCAMREV;
		data &= ~LOONGSON_CFG3_LCAMNUM;
		data &= ~LOONGSON_CFG3_LCAMKW;
		data &= ~LOONGSON_CFG3_LCAMVW;
	}

	c->loongson3_cpucfg_data[2] = data;
}

void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
{
	/* Only engage the logic on Loongson processors. */
	if (!is_loongson(c))
		return;

	/* CPUs with CPUCFG support don't need to synthesize anything. */
	if (cpu_has_cfg())
		goto have_cpucfg_now;

	c->loongson3_cpucfg_data[0] = 0;
	c->loongson3_cpucfg_data[1] = 0;
	c->loongson3_cpucfg_data[2] = 0;

	/* Add CPUCFG features non-discoverable otherwise. */
	switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
		decode_loongson_config6(c);
		probe_uca(c);

		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
			LOONGSON_CFG1_TGTSYNC);
		c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
			LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
			LOONGSON_CFG2_LPM_REV2);
		c->loongson3_cpucfg_data[2] = 0;
		break;

	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
			LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
		c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
			LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1);
		c->loongson3_cpucfg_data[2] |= (
			LOONGSON_CFG3_LCAM_REV1 |
			LOONGSON_CFG3_LCAMNUM_REV1 |
			LOONGSON_CFG3_LCAMKW_REV1 |
			LOONGSON_CFG3_LCAMVW_REV1);
		break;

	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R1:
	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R2:
		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
			LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
		c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
			LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1);
		c->loongson3_cpucfg_data[2] |= (
			LOONGSON_CFG3_LCAM_REV1 |
			LOONGSON_CFG3_LCAMNUM_REV1 |
			LOONGSON_CFG3_LCAMKW_REV1 |
			LOONGSON_CFG3_LCAMVW_REV1);
		break;

	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0:
	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_1:
		decode_loongson_config6(c);
		probe_uca(c);

		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_CNT64 |
			LOONGSON_CFG1_LSLDR0 | LOONGSON_CFG1_LSPREF |
			LOONGSON_CFG1_LSPREFX | LOONGSON_CFG1_LSSYNCI |
			LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
		c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
			LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LBTMMU |
			LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1 |
			LOONGSON_CFG2_LVZ_REV1);
		c->loongson3_cpucfg_data[2] |= (LOONGSON_CFG3_LCAM_REV1 |
			LOONGSON_CFG3_LCAMNUM_REV1 |
			LOONGSON_CFG3_LCAMKW_REV1 |
			LOONGSON_CFG3_LCAMVW_REV1);
		break;

	default:
		/* It is possible that some future Loongson cores still do
		 * not have CPUCFG, so do not emulate anything for these
		 * cores.
		 */
		return;
	}

	/* This feature is set by firmware, but all known Loongson-64 systems
	 * are configured this way.
	 */
	c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_CDMAP;

	/* Patch in dynamically probed bits. */
	patch_cpucfg_sel1(c);
	patch_cpucfg_sel2(c);
	patch_cpucfg_sel3(c);

have_cpucfg_now:
	/* We have usable CPUCFG now, emulated or not.
	 * Announce CPUCFG availability to userspace via hwcap.
	 */
	elf_hwcap |= HWCAP_LOONGSON_CPUCFG;
}