1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
|
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
/* Copyright(c) 2014 - 2020 Intel Corporation */
#ifndef _ICP_QAT_FW_INIT_ADMIN_H_
#define _ICP_QAT_FW_INIT_ADMIN_H_
#include "icp_qat_fw.h"
enum icp_qat_fw_init_admin_cmd_id {
ICP_QAT_FW_INIT_AE = 0,
ICP_QAT_FW_TRNG_ENABLE = 1,
ICP_QAT_FW_TRNG_DISABLE = 2,
ICP_QAT_FW_CONSTANTS_CFG = 3,
ICP_QAT_FW_STATUS_GET = 4,
ICP_QAT_FW_COUNTERS_GET = 5,
ICP_QAT_FW_LOOPBACK = 6,
ICP_QAT_FW_HEARTBEAT_SYNC = 7,
ICP_QAT_FW_HEARTBEAT_GET = 8,
ICP_QAT_FW_COMP_CAPABILITY_GET = 9,
ICP_QAT_FW_DC_CHAIN_INIT = 11,
ICP_QAT_FW_HEARTBEAT_TIMER_SET = 13,
ICP_QAT_FW_TIMER_GET = 19,
ICP_QAT_FW_CNV_STATS_GET = 20,
ICP_QAT_FW_PM_STATE_CONFIG = 128,
ICP_QAT_FW_PM_INFO = 129,
};
enum icp_qat_fw_init_admin_resp_status {
ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0,
ICP_QAT_FW_INIT_RESP_STATUS_FAIL
};
struct icp_qat_fw_init_admin_req {
__u16 init_cfg_sz;
__u8 resrvd1;
__u8 cmd_id;
__u32 resrvd2;
__u64 opaque_data;
__u64 init_cfg_ptr;
union {
struct {
__u16 ibuf_size_in_kb;
__u16 resrvd3;
};
struct {
__u32 int_timer_ticks;
};
struct {
__u32 heartbeat_ticks;
};
__u32 idle_filter;
};
__u32 resrvd4;
} __packed;
struct icp_qat_fw_init_admin_resp {
__u8 flags;
__u8 resrvd1;
__u8 status;
__u8 cmd_id;
union {
__u32 resrvd2;
struct {
__u16 version_minor_num;
__u16 version_major_num;
};
__u32 extended_features;
struct {
__u16 error_count;
__u16 latest_error;
};
};
__u64 opaque_data;
union {
__u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_4];
struct {
__u32 version_patch_num;
__u8 context_id;
__u8 ae_id;
__u16 resrvd4;
__u64 resrvd5;
};
struct {
__u64 req_rec_count;
__u64 resp_sent_count;
};
struct {
__u16 compression_algos;
__u16 checksum_algos;
__u32 deflate_capabilities;
__u32 resrvd6;
__u32 lzs_capabilities;
};
struct {
__u32 cipher_algos;
__u32 hash_algos;
__u16 keygen_algos;
__u16 other;
__u16 public_key_algos;
__u16 prime_algos;
};
struct {
__u64 timestamp;
__u64 resrvd7;
};
struct {
__u32 successful_count;
__u32 unsuccessful_count;
__u64 resrvd8;
};
};
} __packed;
#define ICP_QAT_FW_SYNC ICP_QAT_FW_HEARTBEAT_SYNC
#define ICP_QAT_NUMBER_OF_PM_EVENTS 8
struct icp_qat_fw_init_admin_pm_info {
__u16 max_pwrreq;
__u16 min_pwrreq;
__u16 resvrd1;
__u8 pwr_state;
__u8 resvrd2;
__u32 fusectl0;
struct_group(event_counters,
__u32 sys_pm;
__u32 host_msg;
__u32 unknown;
__u32 local_ssm;
__u32 timer;
);
__u32 event_log[ICP_QAT_NUMBER_OF_PM_EVENTS];
struct_group(pm,
__u32 fw_init;
__u32 pwrreq;
__u32 status;
__u32 main;
__u32 thread;
);
struct_group(ssm,
__u32 pm_enable;
__u32 pm_active_status;
__u32 pm_managed_status;
__u32 pm_domain_status;
__u32 active_constraint;
);
__u32 resvrd3[6];
};
#endif
|
