summaryrefslogtreecommitdiff
path: root/drivers/nvmem/mtk-efuse.c
blob: 9caf046673410129e5fd595e23adceb6bd0772a8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/io.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_device.h>
#include <linux/property.h>

struct mtk_efuse_pdata {
	bool uses_post_processing;
};

struct mtk_efuse_priv {
	void __iomem *base;
};

static int mtk_reg_read(void *context,
			unsigned int reg, void *_val, size_t bytes)
{
	struct mtk_efuse_priv *priv = context;
	void __iomem *addr = priv->base + reg;
	u8 *val = _val;
	int i;

	for (i = 0; i < bytes; i++, val++)
		*val = readb(addr + i);

	return 0;
}

static int mtk_efuse_gpu_speedbin_pp(void *context, const char *id, int index,
				     unsigned int offset, void *data, size_t bytes)
{
	u8 *val = data;

	if (val[0] < 8)
		val[0] = BIT(val[0]);

	return 0;
}

static void mtk_efuse_fixup_dt_cell_info(struct nvmem_device *nvmem,
					 struct nvmem_cell_info *cell)
{
	size_t sz = strlen(cell->name);

	/*
	 * On some SoCs, the GPU speedbin is not read as bitmask but as
	 * a number with range [0-7] (max 3 bits): post process to use
	 * it in OPP tables to describe supported-hw.
	 */
	if (cell->nbits <= 3 &&
	    strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0)
		cell->read_post_process = mtk_efuse_gpu_speedbin_pp;
}

static int mtk_efuse_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct nvmem_device *nvmem;
	struct nvmem_config econfig = {};
	struct mtk_efuse_priv *priv;
	const struct mtk_efuse_pdata *pdata;
	struct platform_device *socinfo;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	pdata = device_get_match_data(dev);
	econfig.add_legacy_fixed_of_cells = true;
	econfig.stride = 1;
	econfig.word_size = 1;
	econfig.reg_read = mtk_reg_read;
	econfig.size = resource_size(res);
	econfig.priv = priv;
	econfig.dev = dev;
	if (pdata->uses_post_processing)
		econfig.fixup_dt_cell_info = &mtk_efuse_fixup_dt_cell_info;
	nvmem = devm_nvmem_register(dev, &econfig);
	if (IS_ERR(nvmem))
		return PTR_ERR(nvmem);

	socinfo = platform_device_register_data(&pdev->dev, "mtk-socinfo",
						PLATFORM_DEVID_AUTO, NULL, 0);
	if (IS_ERR(socinfo))
		dev_info(dev, "MediaTek SoC Information will be unavailable\n");

	platform_set_drvdata(pdev, socinfo);
	return 0;
}

static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
	.uses_post_processing = true,
};

static const struct mtk_efuse_pdata mtk_efuse_pdata = {
	.uses_post_processing = false,
};

static const struct of_device_id mtk_efuse_of_match[] = {
	{ .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
	{ .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
	{ .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },
	{/* sentinel */},
};
MODULE_DEVICE_TABLE(of, mtk_efuse_of_match);

static void mtk_efuse_remove(struct platform_device *pdev)
{
	struct platform_device *socinfo = platform_get_drvdata(pdev);

	if (!IS_ERR_OR_NULL(socinfo))
		platform_device_unregister(socinfo);
}

static struct platform_driver mtk_efuse_driver = {
	.probe = mtk_efuse_probe,
	.remove_new = mtk_efuse_remove,
	.driver = {
		.name = "mediatek,efuse",
		.of_match_table = mtk_efuse_of_match,
	},
};

static int __init mtk_efuse_init(void)
{
	int ret;

	ret = platform_driver_register(&mtk_efuse_driver);
	if (ret) {
		pr_err("Failed to register efuse driver\n");
		return ret;
	}

	return 0;
}

static void __exit mtk_efuse_exit(void)
{
	return platform_driver_unregister(&mtk_efuse_driver);
}

subsys_initcall(mtk_efuse_init);
module_exit(mtk_efuse_exit);

MODULE_AUTHOR("Andrew-CT Chen <andrew-ct.chen@mediatek.com>");
MODULE_DESCRIPTION("Mediatek EFUSE driver");
MODULE_LICENSE("GPL v2");