summaryrefslogtreecommitdiff
path: root/drivers/phy/microchip/lan966x_serdes_regs.h
blob: ea30f64ffd5c8ef458bdf0de96721a45c816d167 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef _LAN966X_SERDES_REGS_H_
#define _LAN966X_SERDES_REGS_H_

#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/bug.h>

enum lan966x_target {
	TARGET_HSIO = 32,
	NUM_TARGETS = 66
};

#define __REG(...)    __VA_ARGS__

/*      HSIO:SD:SD_CFG */
#define HSIO_SD_CFG(g)            __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 0, 0, 1, 4)

#define HSIO_SD_CFG_PHY_RESET                    BIT(27)
#define HSIO_SD_CFG_PHY_RESET_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
#define HSIO_SD_CFG_PHY_RESET_GET(x)\
	FIELD_GET(HSIO_SD_CFG_PHY_RESET, x)

#define HSIO_SD_CFG_TX_RESET                     BIT(18)
#define HSIO_SD_CFG_TX_RESET_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
#define HSIO_SD_CFG_TX_RESET_GET(x)\
	FIELD_GET(HSIO_SD_CFG_TX_RESET, x)

#define HSIO_SD_CFG_TX_RATE                      GENMASK(17, 16)
#define HSIO_SD_CFG_TX_RATE_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
#define HSIO_SD_CFG_TX_RATE_GET(x)\
	FIELD_GET(HSIO_SD_CFG_TX_RATE, x)

#define HSIO_SD_CFG_TX_INVERT                    BIT(15)
#define HSIO_SD_CFG_TX_INVERT_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x)
#define HSIO_SD_CFG_TX_INVERT_GET(x)\
	FIELD_GET(HSIO_SD_CFG_TX_INVERT, x)

#define HSIO_SD_CFG_TX_EN                        BIT(14)
#define HSIO_SD_CFG_TX_EN_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_TX_EN, x)
#define HSIO_SD_CFG_TX_EN_GET(x)\
	FIELD_GET(HSIO_SD_CFG_TX_EN, x)

#define HSIO_SD_CFG_TX_DATA_EN                   BIT(12)
#define HSIO_SD_CFG_TX_DATA_EN_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x)
#define HSIO_SD_CFG_TX_DATA_EN_GET(x)\
	FIELD_GET(HSIO_SD_CFG_TX_DATA_EN, x)

#define HSIO_SD_CFG_TX_CM_EN                     BIT(11)
#define HSIO_SD_CFG_TX_CM_EN_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x)
#define HSIO_SD_CFG_TX_CM_EN_GET(x)\
	FIELD_GET(HSIO_SD_CFG_TX_CM_EN, x)

#define HSIO_SD_CFG_LANE_10BIT_SEL               BIT(10)
#define HSIO_SD_CFG_LANE_10BIT_SEL_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_LANE_10BIT_SEL, x)
#define HSIO_SD_CFG_LANE_10BIT_SEL_GET(x)\
	FIELD_GET(HSIO_SD_CFG_LANE_10BIT_SEL, x)

#define HSIO_SD_CFG_RX_TERM_EN                   BIT(9)
#define HSIO_SD_CFG_RX_TERM_EN_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_RX_TERM_EN, x)
#define HSIO_SD_CFG_RX_TERM_EN_GET(x)\
	FIELD_GET(HSIO_SD_CFG_RX_TERM_EN, x)

#define HSIO_SD_CFG_RX_RESET                     BIT(8)
#define HSIO_SD_CFG_RX_RESET_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_RX_RESET, x)
#define HSIO_SD_CFG_RX_RESET_GET(x)\
	FIELD_GET(HSIO_SD_CFG_RX_RESET, x)

#define HSIO_SD_CFG_RX_RATE                      GENMASK(7, 6)
#define HSIO_SD_CFG_RX_RATE_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_RX_RATE, x)
#define HSIO_SD_CFG_RX_RATE_GET(x)\
	FIELD_GET(HSIO_SD_CFG_RX_RATE, x)

#define HSIO_SD_CFG_RX_PLL_EN                    BIT(5)
#define HSIO_SD_CFG_RX_PLL_EN_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_RX_PLL_EN, x)
#define HSIO_SD_CFG_RX_PLL_EN_GET(x)\
	FIELD_GET(HSIO_SD_CFG_RX_PLL_EN, x)

#define HSIO_SD_CFG_RX_INVERT                    BIT(3)
#define HSIO_SD_CFG_RX_INVERT_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_RX_INVERT, x)
#define HSIO_SD_CFG_RX_INVERT_GET(x)\
	FIELD_GET(HSIO_SD_CFG_RX_INVERT, x)

#define HSIO_SD_CFG_RX_DATA_EN                   BIT(2)
#define HSIO_SD_CFG_RX_DATA_EN_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_RX_DATA_EN, x)
#define HSIO_SD_CFG_RX_DATA_EN_GET(x)\
	FIELD_GET(HSIO_SD_CFG_RX_DATA_EN, x)

#define HSIO_SD_CFG_LANE_LOOPBK_EN               BIT(0)
#define HSIO_SD_CFG_LANE_LOOPBK_EN_SET(x)\
	FIELD_PREP(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
#define HSIO_SD_CFG_LANE_LOOPBK_EN_GET(x)\
	FIELD_GET(HSIO_SD_CFG_LANE_LOOPBK_EN, x)

/*      HSIO:SD:MPLL_CFG */
#define HSIO_MPLL_CFG(g)          __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 8, 0, 1, 4)

#define HSIO_MPLL_CFG_REF_SSP_EN                 BIT(18)
#define HSIO_MPLL_CFG_REF_SSP_EN_SET(x)\
	FIELD_PREP(HSIO_MPLL_CFG_REF_SSP_EN, x)
#define HSIO_MPLL_CFG_REF_SSP_EN_GET(x)\
	FIELD_GET(HSIO_MPLL_CFG_REF_SSP_EN, x)

#define HSIO_MPLL_CFG_REF_CLKDIV2                BIT(17)
#define HSIO_MPLL_CFG_REF_CLKDIV2_SET(x)\
	FIELD_PREP(HSIO_MPLL_CFG_REF_CLKDIV2, x)
#define HSIO_MPLL_CFG_REF_CLKDIV2_GET(x)\
	FIELD_GET(HSIO_MPLL_CFG_REF_CLKDIV2, x)

#define HSIO_MPLL_CFG_MPLL_EN                    BIT(16)
#define HSIO_MPLL_CFG_MPLL_EN_SET(x)\
	FIELD_PREP(HSIO_MPLL_CFG_MPLL_EN, x)
#define HSIO_MPLL_CFG_MPLL_EN_GET(x)\
	FIELD_GET(HSIO_MPLL_CFG_MPLL_EN, x)

#define HSIO_MPLL_CFG_MPLL_MULTIPLIER            GENMASK(6, 0)
#define HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(x)\
	FIELD_PREP(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
#define HSIO_MPLL_CFG_MPLL_MULTIPLIER_GET(x)\
	FIELD_GET(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)

/*      HSIO:SD:SD_STAT */
#define HSIO_SD_STAT(g)           __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 12, 0, 1, 4)

#define HSIO_SD_STAT_MPLL_STATE                  BIT(6)
#define HSIO_SD_STAT_MPLL_STATE_SET(x)\
	FIELD_PREP(HSIO_SD_STAT_MPLL_STATE, x)
#define HSIO_SD_STAT_MPLL_STATE_GET(x)\
	FIELD_GET(HSIO_SD_STAT_MPLL_STATE, x)

#define HSIO_SD_STAT_TX_STATE                    BIT(5)
#define HSIO_SD_STAT_TX_STATE_SET(x)\
	FIELD_PREP(HSIO_SD_STAT_TX_STATE, x)
#define HSIO_SD_STAT_TX_STATE_GET(x)\
	FIELD_GET(HSIO_SD_STAT_TX_STATE, x)

#define HSIO_SD_STAT_TX_CM_STATE                 BIT(2)
#define HSIO_SD_STAT_TX_CM_STATE_SET(x)\
	FIELD_PREP(HSIO_SD_STAT_TX_CM_STATE, x)
#define HSIO_SD_STAT_TX_CM_STATE_GET(x)\
	FIELD_GET(HSIO_SD_STAT_TX_CM_STATE, x)

#define HSIO_SD_STAT_RX_PLL_STATE                BIT(0)
#define HSIO_SD_STAT_RX_PLL_STATE_SET(x)\
	FIELD_PREP(HSIO_SD_STAT_RX_PLL_STATE, x)
#define HSIO_SD_STAT_RX_PLL_STATE_GET(x)\
	FIELD_GET(HSIO_SD_STAT_RX_PLL_STATE, x)

/*      HSIO:HW_CFGSTAT:HW_CFG */
#define HSIO_HW_CFG               __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 0, 0, 1, 4)

#define HSIO_HW_CFG_RGMII_1_CFG                  BIT(15)
#define HSIO_HW_CFG_RGMII_1_CFG_SET(x)\
	(((x) << 15) & GENMASK(15, 15))
#define HSIO_HW_CFG_RGMII_1_CFG_GET(x)\
	FIELD_GET(HSIO_HW_CFG_RGMII_1_CFG, x)

#define HSIO_HW_CFG_RGMII_0_CFG                  BIT(14)
#define HSIO_HW_CFG_RGMII_0_CFG_SET(x)\
	(((x) << 14) & GENMASK(14, 14))
#define HSIO_HW_CFG_RGMII_0_CFG_GET(x)\
	FIELD_GET(HSIO_HW_CFG_RGMII_0_CFG, x)

#define HSIO_HW_CFG_RGMII_ENA                    GENMASK(13, 12)
#define HSIO_HW_CFG_RGMII_ENA_SET(x)\
	(((x) << 12) & GENMASK(13, 12))
#define HSIO_HW_CFG_RGMII_ENA_GET(x)\
	FIELD_GET(HSIO_HW_CFG_RGMII_ENA, x)

#define HSIO_HW_CFG_SD6G_0_CFG                   BIT(11)
#define HSIO_HW_CFG_SD6G_0_CFG_SET(x)\
	(((x) << 11) & GENMASK(11, 11))
#define HSIO_HW_CFG_SD6G_0_CFG_GET(x)\
	FIELD_GET(HSIO_HW_CFG_SD6G_0_CFG, x)

#define HSIO_HW_CFG_SD6G_1_CFG                   BIT(10)
#define HSIO_HW_CFG_SD6G_1_CFG_SET(x)\
	(((x) << 10) & GENMASK(10, 10))
#define HSIO_HW_CFG_SD6G_1_CFG_GET(x)\
	FIELD_GET(HSIO_HW_CFG_SD6G_1_CFG, x)

#define HSIO_HW_CFG_GMII_ENA                     GENMASK(9, 2)
#define HSIO_HW_CFG_GMII_ENA_SET(x)\
	(((x) << 2) & GENMASK(9, 2))
#define HSIO_HW_CFG_GMII_ENA_GET(x)\
	FIELD_GET(HSIO_HW_CFG_GMII_ENA, x)

#define HSIO_HW_CFG_QSGMII_ENA                   GENMASK(1, 0)
#define HSIO_HW_CFG_QSGMII_ENA_SET(x)\
	((x) & GENMASK(1, 0))
#define HSIO_HW_CFG_QSGMII_ENA_GET(x)\
	FIELD_GET(HSIO_HW_CFG_QSGMII_ENA, x)

#endif /* _LAN966X_HSIO_REGS_H_ */