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authorNeal Peacock <kulimandphone3@gmail.com>2013-01-15 07:10:51 +0400
committerAlejandro Mery <amery@geeks.cl>2013-01-24 20:28:54 +0400
commitb8307d3ab21afdefec4478a766a4ff053f2c1b90 (patch)
tree9f16edc90cf190c60ff449f17f71319308ed537f
parent02d99f3ff66919a5700817a35a3c88bf6a574500 (diff)
downloadlinux-sunxi-b8307d3ab21afdefec4478a766a4ff053f2c1b90.tar.xz
block:sunxi-nand: settings updates for various flash chips based on i-onik.de allwinner source dump
This patch updates the settings that were found to be different, note I haven't tested all these changes. Signed-off-by: Neal Peacock <neal@nic-stix.com>
-rwxr-xr-xdrivers/block/sunxi_nand/src/scan/nand_id.c34
1 files changed, 16 insertions, 18 deletions
diff --git a/drivers/block/sunxi_nand/src/scan/nand_id.c b/drivers/block/sunxi_nand/src/scan/nand_id.c
index 73339f67fd83..a05a4be3dcc9 100755
--- a/drivers/block/sunxi_nand/src/scan/nand_id.c
+++ b/drivers/block/sunxi_nand/src/scan/nand_id.c
@@ -194,8 +194,8 @@ struct __NandPhyInfoPar_t SamsungNandTbl[] =
{ {0xec, 0xda, 0xff, 0x15, 0xff, 0xff, 0xff, 0xff }, 2, 4, 64, 1024, 0x0000, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // K9K2G08
{ {0xec, 0xda, 0x10, 0x95, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 2048, 0x0008, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // K9F2G08
{ {0xec, 0xdc, 0xc1, 0x15, 0xff, 0xff, 0xff, 0xff }, 2, 4, 64, 2048, 0x0000, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // K9K4G08
- { {0xec, 0xdc, 0x10, 0x95, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 4096, 0x0018, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // K9F4G08
- { {0xec, 0xd3, 0x51, 0x95, 0xff, 0xff, 0xff, 0xff }, 2, 4, 64, 4096, 0x0018, 974, 30, 0, 0, 0, &PhysicArchiPara0 }, // K9K8G08
+ { {0xec, 0xdc, 0x10, 0x95, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 4096, 0x0008, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // K9F4G08
+ { {0xec, 0xd3, 0x51, 0x95, 0xff, 0xff, 0xff, 0xff }, 2, 4, 64, 4096, 0x0008, 974, 30, 0, 0, 0, &PhysicArchiPara0 }, // K9K8G08
//-----------------------------------------------------------------------------------------------------------------------------------
{ {0xec, 0xd3, 0x50, 0xa6, 0xff, 0xff, 0xff, 0xff }, 1, 4, 128, 4096, 0x0018, 974, 30, 0, 0, 0, &PhysicArchiPara1 }, // K9F8G08
{ {0xec, 0xd5, 0x51, 0xa6, 0xff, 0xff, 0xff, 0xff }, 2, 4, 128, 4096, 0x0038, 974, 30, 0, 0, 0, &PhysicArchiPara1 }, // K9KAG08
@@ -273,11 +273,9 @@ struct __NandPhyInfoPar_t HynixNandTbl[] =
{ {0xad, 0xd7, 0x94, 0x9A, 0xff, 0xff, 0xff, 0xff }, 1, 16, 256, 2048, 0x0008, 950, 30, 2, 0, 0, &PhysicArchiPara3 }, // H27UBG8T2A H27UCG8U5(D)A H27UDG8VF(D)A
{ {0xad, 0xde, 0xd5, 0x9A, 0xff, 0xff, 0xff, 0xff }, 2, 16, 256, 2048, 0x0008, 950, 30, 2, 0, 0, &PhysicArchiPara3 }, // H27UDG8V5A
{ {0xad, 0xd7, 0x94, 0x25, 0xff, 0xff, 0xff, 0xff }, 1, 8, 128, 8192, 0x0008, 974, 30, 2, 0, 0, &PhysicArchiPara3 }, // H27UBG8T2M
- { {0xad, 0xde, 0x94, 0xd2, 0xff, 0xff, 0xff, 0xff }, 1, 16, 256, 4096, 0x0188, 950, 15, 2, 0x000604, 0, &PhysicArchiPara3 }, // H27UCG8T2M
- { {0xad, 0xd7, 0x18, 0x8d, 0xff, 0xff, 0xff, 0xff }, 1, 8, 256, 4096, 0x0188, 950, 15, 3, 0x000604, 0, &PhysicArchiPara3 }, // H27UBG8M2A
- { {0xad, 0xd7, 0x94, 0xda, 0xff, 0xff, 0xff, 0xff }, 1, 16, 256, 2048, 0x0188, 950, 15, 3, 0x010604, 0, &PhysicArchiPara3 }, // H27UBG8M2A
-
-
+ { {0xad, 0xde, 0x94, 0xd2, 0xff, 0xff, 0xff, 0xff }, 1, 16, 256, 4096, 0x0188, 950, 30, 2, 0x000604, 0, &PhysicArchiPara3 }, // H27UCG8T2M
+ { {0xad, 0xd7, 0x18, 0x8d, 0xff, 0xff, 0xff, 0xff }, 1, 8, 256, 4096, 0x0188, 950, 30, 3, 0x000604, 0, &PhysicArchiPara3 }, // H27UBG8M2A
+ { {0xad, 0xd7, 0x94, 0xda, 0xff, 0xff, 0xff, 0xff }, 1, 16, 256, 2048, 0x0188, 950, 30, 3, 0x010604, 0, &PhysicArchiPara3 }, // H27UBG8M2A
{ {0xad, 0xde, 0x94, 0xda, 0x74, 0xff, 0xff, 0xff }, 1, 16, 256, 4096, 0x0188, 960, 40, 4, 0x020708, 0, &PhysicArchiPara3 }, // H27UCG8T2A
{ {0xad, 0xd7, 0x94, 0x91, 0x60, 0xff, 0xff, 0xff }, 1, 16, 256, 2048, 0x0188, 960, 40, 4, 0x030708, 0, &PhysicArchiPara3 }, // H27UBG8T2C
//---------------------------------------------------------------------------------------------------------------------------
@@ -309,9 +307,9 @@ struct __NandPhyInfoPar_t ToshibaNandTbl[] =
{ {0x98, 0xd7, 0x94, 0x32, 0xff, 0xff, 0xff, 0xff }, 1, 16, 128, 4096, 0x0008, 918, 25, 2, 0, 0, &PhysicArchiPara8}, // TH58NVG5D2FTA00 TH58NVG6D2FTA20
{ {0x98, 0xd7, 0x95, 0x32, 0xff, 0xff, 0xff, 0xff }, 2, 16, 128, 4096, 0x0008, 454, 25, 1, 0, 0, &PhysicArchiPara8}, // TH58NVG6D2ETA20
//-------------------------------------------------------------------------------------------------------------------------
- { {0x98, 0xde, 0x94, 0x82, 0x76, 0xff, 0xff, 0xff }, 1, 16, 256, 4096, 0x0588, 918, 25, 4, 0x100504, 0, &PhysicArchiPara9}, // TH58NVG6D2ETA20
- { {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0xff, 0xff }, 1, 16, 128, 4096, 0x0588, 918, 25, 4, 0x100504, 0, &PhysicArchiPara9}, // TH58NVG5D2HTA20
- { {0x98, 0xd5, 0x84, 0x32, 0x72, 0x56, 0xff, 0xff }, 1, 16, 128, 2048, 0x0580, 918, 25, 4, 0x100504, 0, &PhysicArchiPara9}, // TH58NVG4D2HTA20
+ { {0x98, 0xde, 0x94, 0x82, 0x76, 0xff, 0xff, 0xff }, 1, 16, 256, 4096, 0x0588, 918, 40, 4, 0x100504, 0, &PhysicArchiPara9}, // TH58NVG6D2ETA20
+ { {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0xff, 0xff }, 1, 16, 128, 4096, 0x0588, 918, 40, 4, 0x100504, 0, &PhysicArchiPara9}, // TH58NVG5D2HTA20
+ { {0x98, 0xd5, 0x84, 0x32, 0x72, 0x56, 0xff, 0xff }, 1, 16, 128, 2048, 0x0580, 918, 40, 4, 0x100504, 0, &PhysicArchiPara9}, // TH58NVG4D2HTA20
//-------------------------------------------------------------------------------------------------------------------------
{ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0, 0 }, // NULL
};
@@ -324,10 +322,10 @@ struct __NandPhyInfoPar_t MicronNandTbl[] =
{
// NAND_CHIP_ID DieCnt SecCnt PagCnt BlkCnt OpOpt DatBlk Freq EccMode ReadRetry OperationPar
//-------------------------------------------------------------------------------------------------------------------------
- { {0x2c, 0xda, 0xff, 0x15, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 2048, 0x0010, 974, 25, 0, 0, 0, &PhysicArchiPara4 }, // MT29F2G08AAC, JS29F02G08AAN
- { {0x2c, 0xdc, 0xff, 0x15, 0xff, 0xff, 0xff, 0xff }, 2, 4, 64, 2048, 0x0010, 974, 25, 0, 0, 0, &PhysicArchiPara4 }, // MT29F4G08BAB, MT29F8G08FAB, JS29F04G08BAN, JS29F08G08FAN
- { {0x2c, 0xdc, 0x90, 0x95, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 4096, 0x0018, 974, 25, 0, 0, 0, &PhysicArchiPara4 }, // MT29F4G08AAA, MT29F8G08DAA, JS29F04G08AAN
- { {0x2c, 0xd3, 0xd1, 0x95, 0xff, 0xff, 0xff, 0xff }, 2, 4, 64, 4096, 0x0018, 974, 25, 0, 0, 0, &PhysicArchiPara4 }, // MT29F8G08BAB, MT29F16G08FAB, JS29F08G08BAN, JS29F16G08FAN
+ { {0x2c, 0xda, 0xff, 0x15, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 2048, 0x0000, 974, 25, 0, 0, 0, &PhysicArchiPara4 }, // MT29F2G08AAC, JS29F02G08AAN
+ { {0x2c, 0xdc, 0xff, 0x15, 0xff, 0xff, 0xff, 0xff }, 2, 4, 64, 2048, 0x0000, 974, 25, 0, 0, 0, &PhysicArchiPara4 }, // MT29F4G08BAB, MT29F8G08FAB, JS29F04G08BAN, JS29F08G08FAN
+ { {0x2c, 0xdc, 0x90, 0x95, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 4096, 0x0008, 974, 25, 0, 0, 0, &PhysicArchiPara4 }, // MT29F4G08AAA, MT29F8G08DAA, JS29F04G08AAN
+ { {0x2c, 0xd3, 0xd1, 0x95, 0xff, 0xff, 0xff, 0xff }, 2, 4, 64, 4096, 0x0008, 974, 25, 0, 0, 0, &PhysicArchiPara4 }, // MT29F8G08BAB, MT29F16G08FAB, JS29F08G08BAN, JS29F16G08FAN
//-------------------------------------------------------------------------------------------------------------------------
{ {0x2c, 0xdc, 0x84, 0x25, 0xff, 0xff, 0xff, 0xff }, 1, 4, 128, 2048, 0x0000, 974, 20, 0, 0, 0, &PhysicArchiPara4 }, // MT29F4G08MAA, MT29F8G08QAA
{ {0x2c, 0xd3, 0x85, 0x25, 0xff, 0xff, 0xff, 0xff }, 2, 4, 128, 2048, 0x0000, 974, 20, 0, 0, 0, &PhysicArchiPara4 }, // MT29F16GTAA
@@ -343,9 +341,9 @@ struct __NandPhyInfoPar_t MicronNandTbl[] =
{ {0x2c, 0xd9, 0xd5, 0x3e, 0xff, 0xff, 0xff, 0xff }, 2, 8, 128, 8192, 0x0008, 950, 30, 2, 0, 0, &PhysicArchiPara4 }, // MT29F128G08,
{ {0x2c, 0x68, 0x04, 0x46, 0xff, 0xff, 0xff, 0xff }, 1, 8, 256, 4096, 0x0208, 950, 30, 2, 0, 0, &PhysicArchiPara4 }, // MT29F32G08CBABA
{ {0x2c, 0x88, 0x05, 0xC6, 0xff, 0xff, 0xff, 0xff }, 2, 8, 256, 4096, 0x0208, 950, 30, 2, 0, 0, &PhysicArchiPara4 }, // MT29F128G08CJABA
- { {0x2c, 0x88, 0x04, 0x4B, 0xff, 0xff, 0xff, 0xff }, 1, 16, 256, 4096, 0x0208, 950, 30, 2, 0, 0, &PhysicArchiPara4 }, // MT29F64G08CBAAA
- { {0x2c, 0x68, 0x04, 0x4A, 0xff, 0xff, 0xff, 0xff }, 1, 8, 256, 4096, 0x0208, 950, 30, 2, 0, 0, &PhysicArchiPara4 }, // MT29F32G08CBACA
- { {0x2c, 0x48, 0x04, 0x4A, 0xff, 0xff, 0xff, 0xff }, 1, 8, 256, 2048, 0x0208, 950, 30, 2, 0, 0, &PhysicArchiPara4 }, // MT29F16G08CBACA
+ { {0x2c, 0x88, 0x04, 0x4B, 0xff, 0xff, 0xff, 0xff }, 1, 16, 256, 4096, 0x0208, 950, 40, 2, 0, 0, &PhysicArchiPara4 }, // MT29F64G08CBAAA
+ { {0x2c, 0x68, 0x04, 0x4A, 0xff, 0xff, 0xff, 0xff }, 1, 8, 256, 4096, 0x0208, 950, 40, 2, 0, 0, &PhysicArchiPara4 }, // MT29F32G08CBACA
+ { {0x2c, 0x48, 0x04, 0x4A, 0xff, 0xff, 0xff, 0xff }, 1, 8, 256, 2048, 0x0208, 950, 40, 2, 0, 0, &PhysicArchiPara4 }, // MT29F16G08CBACA
{ {0x2c, 0x48, 0x04, 0x46, 0xff, 0xff, 0xff, 0xff }, 1, 8, 256, 2048, 0x0208, 950, 30, 2, 0, 0, &PhysicArchiPara4 }, // MT29F16G08CBABA
{ {0x2c, 0x64, 0x44, 0x4B, 0xA9, 0xff, 0xff, 0xff }, 1, 16, 256, 4096, 0x0208, 950, 40, 4, 0, 0, &PhysicArchiPara4 }, // MT29F64G08CBABA
//-------------------------------------------------------------------------------------------------------------------------
@@ -381,7 +379,7 @@ struct __NandPhyInfoPar_t StNandTbl[] =
{
// NAND_CHIP_ID DieCnt SecCnt PagCnt BlkCnt OpOpt DatBlk Freq EccMode ReadRetry OperationPar
//-------------------------------------------------------------------------------------------------------------------------
- { {0x20, 0xf1, 0x80, 0x15, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x0010, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // NAND01GW3B
+ { {0x20, 0xf1, 0x80, 0x15, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x0000, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // NAND01GW3B
{ {0x20, 0xf1, 0x00, 0x1d, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x0000, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // NAND01G001
{ {0x20, 0xda, 0x80, 0x15, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 2048, 0x0000, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // NAND02GW3B
{ {0x20, 0xda, 0x10, 0x95, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 2048, 0x0000, 974, 15, 0, 0, 0, &PhysicArchiPara0 }, // NAND02GW3B2DN6