diff options
author | Andy Hu <andy.hu@starfivetech.com> | 2023-12-21 17:24:35 +0300 |
---|---|---|
committer | Andy Hu <andy.hu@starfivetech.com> | 2023-12-21 17:24:35 +0300 |
commit | a77eaf219c34156e52298a6ab2357aaa4251df8b (patch) | |
tree | 9e590a7df0c0cdad5c36db91c8cb27e96d1c4dcf | |
parent | 96bb7d94388fb138df06b7e4b10ce228fe422e08 (diff) | |
parent | 7ad9e62e93481d0356efd7c4e399959ba7cbe8ee (diff) | |
download | linux-a77eaf219c34156e52298a6ab2357aaa4251df8b.tar.xz |
Merge tag 'JH7110_SDK_6.1_v5.10.3' into vf2-6.1.y-develJH7110_VF2_6.1_v5.10.3
-rwxr-xr-x[-rw-r--r--] | drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.h | 2 |
2 files changed, 11 insertions, 5 deletions
diff --git a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c index fbb5e93148fb..00c1cbc5910b 100644..100755 --- a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c +++ b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c @@ -68,6 +68,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "kernel_compatibility.h" #include <linux/pm_runtime.h> +#include <linux/of.h> struct sf7110_cfg sf_cfg_t = {0,}; @@ -202,9 +203,7 @@ void SysDevHost_Cache_Maintenance(IMG_HANDLE hSysData, return; } len = (unsigned long)(sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr); - //printk("FF cop:%d, s:%llx, len:%lx\n", eRequestType, sCPUPhysStart.uiAddr, len); - //if(len < 64) - // dump_stack(); + switch (eRequestType) { case PVRSRV_CACHE_OP_INVALIDATE: @@ -250,6 +249,7 @@ static int create_sf7110_cfg(struct device *dev) return -ENOMEM; psf->gpu_reg_start = STARFIVE_7110_GPU_PBASE; psf->gpu_reg_size = STARFIVE_7110_GPU_SIZE; + psf->rate = RGX_STARFIVE_7100_CORE_CLOCK_SPEED; psf->clk_apb = devm_clk_get_optional(dev, "clk_apb"); if (IS_ERR(psf->clk_apb)) { @@ -299,6 +299,10 @@ static int create_sf7110_cfg(struct device *dev) goto err_gpu_unmap; } + if (of_find_node_by_path("/opp-table-0/opp-1250000000")) { + psf->rate = RGX_STARFIVE_7100_CORE_CLOCK_SPEED_BIN2; + } + psf->runtime_resume = sys_gpu_runtime_resume; psf->runtime_suspend = sys_gpu_runtime_suspend; @@ -312,7 +316,7 @@ void u0_img_gpu_enable(void) { clk_prepare_enable(sf_cfg_t.clk_apb); clk_prepare_enable(sf_cfg_t.clk_rtc); - clk_set_rate(sf_cfg_t.clk_div, RGX_STARFIVE_7100_CORE_CLOCK_SPEED); + clk_set_rate(sf_cfg_t.clk_div, sf_cfg_t.rate); clk_prepare_enable(sf_cfg_t.clk_core); clk_prepare_enable(sf_cfg_t.clk_sys); @@ -437,7 +441,6 @@ PVRSRV_ERROR SysDevInit(void *pvOSDevice, PVRSRV_DEVICE_CONFIG **ppsDevConfig) /* * Setup RGX specific timing data */ - gsRGXTimingInfo.ui32CoreClockSpeed = RGX_STARFIVE_7100_CORE_CLOCK_SPEED; gsRGXTimingInfo.bEnableActivePM = IMG_TRUE; gsRGXTimingInfo.bEnableRDPowIsland = IMG_TRUE; gsRGXTimingInfo.ui32ActivePMLatencyms = SYS_RGX_ACTIVE_POWER_LATENCY_MS; @@ -497,6 +500,7 @@ PVRSRV_ERROR SysDevInit(void *pvOSDevice, PVRSRV_DEVICE_CONFIG **ppsDevConfig) return PVRSRV_ERROR_BAD_MAPPING; } gsDevices[0].hSysData = &sf_cfg_t; + gsRGXTimingInfo.ui32CoreClockSpeed = sf_cfg_t.rate; pm_runtime_enable(sf_cfg_t.dev); /* power management on HW system */ diff --git a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.h b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.h index 435f6373a5f4..bdb095511676 100644 --- a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.h +++ b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.h @@ -76,6 +76,7 @@ struct sf7110_cfg { struct device *dev; SYS_DEV_CLK_GET runtime_resume; SYS_DEV_CLK_GET runtime_suspend; + unsigned long rate; }; #define mk_crg_offset(x) ((x) - (U0_SYS_CRG__SAIF_BD_APBS__BASE_ADDR)) @@ -85,6 +86,7 @@ struct sf7110_cfg { #define SYS_RGX_ACTIVE_POWER_LATENCY_MS (80000) #else #define RGX_STARFIVE_7100_CORE_CLOCK_SPEED (594.0 * 1000 * 1000)//maybe 400M? +#define RGX_STARFIVE_7100_CORE_CLOCK_SPEED_BIN2 (396.0 * 1000 * 1000) #define SYS_RGX_ACTIVE_POWER_LATENCY_MS (100) #endif |