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| author | Ziv Xu <ziv.xu@starfivetech.com> | 2024-01-18 13:35:46 +0300 |
|---|---|---|
| committer | Ziv Xu <ziv.xu@starfivetech.com> | 2024-01-19 11:23:25 +0300 |
| commit | 08fc3d8e4bd0a843a5aec80f481671fad3f9a378 (patch) | |
| tree | 2823c39d0a4252cf4f0b41e6a69e7ed43768a4e8 | |
| parent | c1d57ddbd8dbd3a27bbb79350e5eebf9efa5dcc9 (diff) | |
| download | linux-08fc3d8e4bd0a843a5aec80f481671fad3f9a378.tar.xz | |
driver: mtd: gigadevice: add gd25lq256d 32M flash support
add gd25lq256d 32M flash support
Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
| -rw-r--r-- | drivers/mtd/spi-nor/gigadevice.c | 47 |
1 files changed, 33 insertions, 14 deletions
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c index 70c816ded7fa..36352a90d70b 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -8,18 +8,33 @@ #include "core.h" -static void gd25q256_default_init(struct spi_nor *nor) +static void gigadevice_default_init(struct spi_nor *nor) { - /* use Quad page program */ + /* Use Quad Page Program */ nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_1_4], SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); } +static void gd25q256_default_init(struct spi_nor *nor) +{ + /* + * Some manufacturer like GigaDevice may use different + * bit to set QE on different memories, so the MFR can't + * indicate the quad_enable method for this case, we need + * to set it in the default_init fixup hook. + */ + nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; +} + static struct spi_nor_fixups gd25q256_fixups = { .default_init = gd25q256_default_init, }; +static struct spi_nor_fixups gigadevice_fixups = { + .default_init = gigadevice_default_init, +}; + static const struct flash_info gigadevice_parts[] = { { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -28,24 +43,29 @@ static const struct flash_info gigadevice_parts[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_SKIP_SFDP | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_SKIP_SFDP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + .fixups = &gigadevice_fixups }, { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { "gd25lq256d", INFO(0xc86019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_SKIP_SFDP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + .fixups = &gigadevice_fixups }, { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | - SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6) + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | + SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6) .fixups = &gd25q256_fixups }, }; @@ -53,5 +73,4 @@ const struct spi_nor_manufacturer spi_nor_gigadevice = { .name = "gigadevice", .parts = gigadevice_parts, .nparts = ARRAY_SIZE(gigadevice_parts), - .fixups = &gd25q256_fixups, }; |