Merge tag 'JH7110_SDK_515_v5.10.6' into vf2-515-devel

6 files changed, 53 insertions, 23 deletions

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 5c8485ea8859..604fdeecd1da 100755
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -757,7 +757,7 @@
     nor_flash: nor-flash@0 {
     compatible = "jedec,spi-nor";
     reg=<0>;
-    cdns,read-delay = <5>;
+    cdns,read-delay = <3>;
     spi-max-frequency = <100000000>;
     cdns,tshsl-ns = <1>;
     cdns,tsd2d-ns = <1>;
diff --git a/arch/riscv/configs/starfive_jh7110_defconfig b/arch/riscv/configs/starfive_jh7110_defconfig
index 036dcdcc6e02..35fcc1285b2f 100644
--- a/arch/riscv/configs/starfive_jh7110_defconfig
+++ b/arch/riscv/configs/starfive_jh7110_defconfig
@@ -34,6 +34,7 @@ CONFIG_RISCV_SBI_CPUIDLE=y
 # CONFIG_SECCOMP is not set
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
+CONFIG_BINFMT_MISC=y
 CONFIG_PAGE_REPORTING=y
 CONFIG_CMA=y
 CONFIG_NET=y
diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_video.c b/drivers/media/platform/starfive/v4l2_driver/stf_video.c
index 8a5e5a846f96..38876d4329c1 100644
--- a/drivers/media/platform/starfive/v4l2_driver/stf_video.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_video.c
@@ -216,6 +216,11 @@ static int __video_try_fmt(struct stfcamss_video *video,
 				pix->height, fi->bpp[0]);
 		st_info(ST_VIDEO, "i = %d, s = 0x%x\n", i, pix->sizeimage);
 	}
+
+	if (stf_vin_map_isp_pad(video->id, STF_ISP_PAD_SRC)
+		== STF_ISP_PAD_SRC_SCD_Y)
+		pix->sizeimage = ISP_SCD_Y_BUFFER_SIZE;
+
 	return 0;
 }
 
@@ -285,11 +290,6 @@ static int video_queue_setup(struct vb2_queue *q,
 		if (!sizes[0])
 			st_err(ST_VIDEO, "%s: error size is zero!!!\n", __func__);
 	}
-	if ((stf_vin_map_isp_pad(video->id, STF_ISP_PAD_SRC)
-		== STF_ISP_PAD_SRC_SCD_Y) &&
-		sizes[0] < ISP_SCD_Y_BUFFER_SIZE) {
-		sizes[0] = ISP_SCD_Y_BUFFER_SIZE;
-	}
 
 	st_info(ST_VIDEO, "%s, planes = %d, size = %d\n",
 			__func__, *num_planes, sizes[0]);
diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_vin.c b/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
index dc30b018e684..8be849aab420 100644
--- a/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
@@ -362,7 +362,10 @@ static void vin_buf_l2cache_flush(struct vin_output *output)
 
 	if (!list_empty(&output->pending_bufs)) {
 		list_for_each_entry(buffer, &output->pending_bufs, queue) {
-			sifive_l2_flush64_range(buffer->addr[0], buffer->sizeimage);
+			if (buffer->sizeimage > STF_VIN_CRITICAL_CACHE_SIZE)
+				sifive_ccache_flush_entire();
+			else
+				sifive_l2_flush64_range(buffer->addr[0], buffer->sizeimage);
 		}
 	}
 }
@@ -1171,8 +1174,12 @@ static void vin_buffer_done(struct vin_line *line, struct vin_params *params)
 		 * which will not update cache by default.
 		 * Flush L2 cache to make sure data is updated.
 		 */
-		if (ready_buf->vb.vb2_buf.memory == VB2_MEMORY_MMAP)
-			sifive_l2_flush64_range(ready_buf->addr[0], ready_buf->sizeimage);
+		if (ready_buf->vb.vb2_buf.memory == VB2_MEMORY_MMAP) {
+			if (ready_buf->sizeimage > STF_VIN_CRITICAL_CACHE_SIZE)
+				sifive_ccache_flush_entire();
+			else
+				sifive_l2_flush64_range(ready_buf->addr[0], ready_buf->sizeimage);
+		}
 
 		vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
 	}
diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_vin.h b/drivers/media/platform/starfive/v4l2_driver/stf_vin.h
index 6b331b738440..812e7a91ed9f 100644
--- a/drivers/media/platform/starfive/v4l2_driver/stf_vin.h
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_vin.h
@@ -21,6 +21,8 @@
 #define STF_VIN_PAD_SRC    1
 #define STF_VIN_PADS_NUM   2
 
+#define STF_VIN_CRITICAL_CACHE_SIZE 0x80000
+
 struct vin2_format {
 	u32 code;
 	u8 bpp;
@@ -169,6 +171,7 @@ struct stf_vin2_dev {
 };
 
 extern void sifive_l2_flush64_range(unsigned long start, unsigned long len);
+extern void sifive_ccache_flush_entire(void);
 extern int stf_vin_subdev_init(struct stfcamss *stfcamss);
 extern int stf_vin_register(struct stf_vin2_dev *vin_dev,
 		struct v4l2_device *v4l2_dev);
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
index 70c816ded7fa..36352a90d70b 100644
--- a/drivers/mtd/spi-nor/gigadevice.c
+++ b/drivers/mtd/spi-nor/gigadevice.c
@@ -8,18 +8,33 @@
 
 #include "core.h"
 
-static void gd25q256_default_init(struct spi_nor *nor)
+static void gigadevice_default_init(struct spi_nor *nor)
 {
-	/* use Quad page program */
+	/* Use Quad Page Program */
 	nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
 	spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_1_4],
 				SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
 }
 
+static void gd25q256_default_init(struct spi_nor *nor)
+{
+	/*
+	 * Some manufacturer like GigaDevice may use different
+	 * bit to set QE on different memories, so the MFR can't
+	 * indicate the quad_enable method for this case, we need
+	 * to set it in the default_init fixup hook.
+	 */
+	nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+}
+
 static struct spi_nor_fixups gd25q256_fixups = {
 	.default_init = gd25q256_default_init,
 };
 
+static struct spi_nor_fixups gigadevice_fixups = {
+	.default_init = gigadevice_default_init,
+};
+
 static const struct flash_info gigadevice_parts[] = {
 	{ "gd25q16", INFO(0xc84015, 0, 64 * 1024,  32,
 			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
@@ -28,24 +43,29 @@ static const struct flash_info gigadevice_parts[] = {
 			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
 	{ "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
-			   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
 	{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
 			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
 	{ "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
-			    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			    SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
 	{ "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
-			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_SKIP_SFDP |
-			     SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			  SPI_NOR_SKIP_SFDP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+		.fixups = &gigadevice_fixups },
 	{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
-			   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+	{ "gd25lq256d", INFO(0xc86019, 0, 64 * 1024, 512,
+			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			  SPI_NOR_SKIP_SFDP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+		.fixups = &gigadevice_fixups },
 	{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
-			   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			   SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
-			   SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
+			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			  SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
+			  SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
 		.fixups = &gd25q256_fixups },
 };
 
@@ -53,5 +73,4 @@ const struct spi_nor_manufacturer spi_nor_gigadevice = {
 	.name = "gigadevice",
 	.parts = gigadevice_parts,
 	.nparts = ARRAY_SIZE(gigadevice_parts),
-	.fixups = &gd25q256_fixups,
 };