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| author | Kevin Xie <kevin.xie@starfivetech.com> | 2024-01-08 14:06:10 +0300 |
|---|---|---|
| committer | Hal Feng <hal.feng@starfivetech.com> | 2024-01-18 13:08:48 +0300 |
| commit | 1dee27e7fdb4c17277429a7e8ba4281acf87bc9f (patch) | |
| tree | 8ad9e84a8e7826155fb27824ba4378ed48327768 | |
| parent | d4ff73d0f773c26eb03ead289660f65c2a63ad3a (diff) | |
| download | linux-1dee27e7fdb4c17277429a7e8ba4281acf87bc9f.tar.xz | |
PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value
Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum
waiting time between exit from a conventional reset and sending the
first configuration request to the device.
As described in PCI base specification r6.0, section 6.6.1 <Conventional
Reset>, there are two different use cases of the value:
- "With a Downstream Port that does not support Link speeds greater
than 5.0 GT/s, software must wait a minimum of 100 ms following exit
from a Conventional Reset before sending a Configuration Request to
the device immediately below that Port."
- "With a Downstream Port that supports Link speeds greater than
5.0 GT/s, software must wait a minimum of 100 ms after Link training
completes before sending a Configuration Request to the device
immediately below that Port."
Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
| -rw-r--r-- | drivers/pci/pci.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 39a8932dc340..952b8a23f5df 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -19,6 +19,22 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * As described in PCI base specification r6.0, section 6.6.1 <Conventional + * Reset>, there are two different use cases of the value: + * + * - "With a Downstream Port that does not support Link speeds greater + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit + * from a Conventional Reset before sending a Configuration Request to + * the device immediately below that Port." + * + * - "With a Downstream Port that supports Link speeds greater than + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; |