diff options
| author | Genevieve Chan <genevieve.chan@starfivetech.com> | 2023-08-09 08:27:58 +0300 |
|---|---|---|
| committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2023-12-04 06:00:16 +0300 |
| commit | 2237a898e0517a646f22af1e39972481fa7fee70 (patch) | |
| tree | 159040a72337e54c453650acc844192fde03005a | |
| parent | 47a15e92f1df8c63fc39f5b878ff074eacbd21b9 (diff) | |
| download | linux-2237a898e0517a646f22af1e39972481fa7fee70.tar.xz | |
riscv: dts: starfive: Enable sscofpmf extension support
Add sscofpmf extension support and interrupt register.
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
| -rwxr-xr-x[-rw-r--r--] | arch/riscv/boot/dts/starfive/dubhe.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi index 49d36e1bbc9e..95caf3cbf794 100644..100755 --- a/arch/riscv/boot/dts/starfive/dubhe.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi @@ -25,7 +25,7 @@ i-tlb-size = <32>; mmu-type = "riscv,sv48"; reg = <0x0>; - riscv,isa = "rv64imafdcbhn"; + riscv,isa = "rv64imafdcbhn_sscofpmf"; tlb-split; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -47,7 +47,7 @@ i-tlb-size = <32>; mmu-type = "riscv,sv48"; reg = <0x1>; - riscv,isa = "rv64imafdcbhn"; + riscv,isa = "rv64imafdcbhn_sscofpmf"; tlb-split; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -161,6 +161,8 @@ pmu { compatible = "riscv,pmu"; + interrupts-extended = <&cpu0_intc 13>, + <&cpu1_intc 13>; riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>, <0x00006 0x0000 0xB>, <0x00008 0x0000 0x10>, |