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| author | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2023-11-15 17:48:44 +0300 |
|---|---|---|
| committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2023-12-04 06:00:17 +0300 |
| commit | 26e10f0c2845783c1a395d750f2dd02e0f13daf7 (patch) | |
| tree | a97e6d2ae592aab526693de8959a460133ed7590 | |
| parent | bb6f3b1ceb5ce22dba1e6695ff681a9089ee8bc2 (diff) | |
| download | linux-26e10f0c2845783c1a395d750f2dd02e0f13daf7.tar.xz | |
riscv: dts: starfive: dubhe: Update Dubhe CPU compatible strings
Change to "starfive,dubhe-80" and "starfive,dubhe-90" compatible strings.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/dubhe.dtsi | 1 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe80.dtsi | 2 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe90.dtsi | 2 |
3 files changed, 4 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi index 53465859b661..bddc2ccfedea 100755 --- a/arch/riscv/boot/dts/starfive/dubhe.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi @@ -13,7 +13,6 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "starfive,dubhe", "riscv"; device_type = "cpu"; mmu-type = "riscv,sv48"; reg = <0x0>; diff --git a/arch/riscv/boot/dts/starfive/dubhe80.dtsi b/arch/riscv/boot/dts/starfive/dubhe80.dtsi index 2eeb2d28655c..92547c5f5860 100644 --- a/arch/riscv/boot/dts/starfive/dubhe80.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe80.dtsi @@ -4,6 +4,7 @@ #include "dubhe.dtsi" &cpu0 { + compatible = "starfive,dubhe-80", "riscv"; d-cache-block-size = <64>; d-cache-sets = <512>; d-cache-size = <32768>; @@ -17,6 +18,7 @@ }; &cpu1 { + compatible = "starfive,dubhe-80", "riscv"; d-cache-block-size = <64>; d-cache-sets = <512>; d-cache-size = <32768>; diff --git a/arch/riscv/boot/dts/starfive/dubhe90.dtsi b/arch/riscv/boot/dts/starfive/dubhe90.dtsi index 54297ca6d805..399270bdcf9f 100644 --- a/arch/riscv/boot/dts/starfive/dubhe90.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe90.dtsi @@ -4,6 +4,7 @@ #include "dubhe.dtsi" &cpu0 { + compatible = "starfive,dubhe-90", "riscv"; d-cache-block-size = <64>; d-cache-sets = <1024>; d-cache-size = <65536>; @@ -17,6 +18,7 @@ }; &cpu1 { + compatible = "starfive,dubhe-90", "riscv"; d-cache-block-size = <64>; d-cache-sets = <1024>; d-cache-size = <65536>; |