perf vendor events riscv: Update JSON array syntax for Starfive Dubhe Perf

This patch updates pmu-events json array syntax.

Signed-off-by: Yang Lee <yang.lee@starfivetech.com>

8 files changed, 178 insertions, 178 deletions

diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/cache.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/cache.json
index 4d2f22817504..a740c298859b 100644
--- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/cache.json
+++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/cache.json
@@ -2,51 +2,51 @@
   {
     "EventName": "L2C_LD_REQ",
     "EventCode": "0xB2",
-    "BriefDescription": "Load request L2C",
+    "BriefDescription": "Load request L2C"
   },
   {
     "EventName": "L2C_LD_MISS",
     "EventCode": "0xB3",
-    "BriefDescription": "Load miss L2C",
+    "BriefDescription": "Load miss L2C"
   },
   {
     "EventName": "L2C_ST_REQ",
     "EventCode": "0xB4",
-    "BriefDescription": "Store request L2C",
+    "BriefDescription": "Store request L2C"
   },
   {
     "EventName": "L2C_ST_MISS",
     "EventCode": "0xB5",
-    "BriefDescription": "Store miss L2C",
+    "BriefDescription": "Store miss L2C"
   },
   {
     "EventName": "L2C_REQ_TO_TL",
     "EventCode": "0xB6",
-    "BriefDescription": "L2C request TL",
+    "BriefDescription": "L2C request TL"
   },
   {
     "EventName": "L2C_EVICT",
     "EventCode": "0xB7",
-    "BriefDescription": "L2C eviction",
+    "BriefDescription": "L2C eviction"
   },
   {
     "EventName": "L2C_ORQ_FULL",
     "EventCode": "0xB8",
-    "BriefDescription": "ORQ (outstanding read queue) full",
+    "BriefDescription": "ORQ (outstanding read queue) full"
   },
   {
     "EventName": "L2C_CRQ_STALL",
     "EventCode": "0xB9",
-    "BriefDescription": "CRQ (core read queue) stall (for each core)",
+    "BriefDescription": "CRQ (core read queue) stall (for each core)"
   },
   {
     "EventName": "L2C_CRQ_FULL",
     "EventCode": "0xBA",
-    "BriefDescription": "CRQ full",
+    "BriefDescription": "CRQ full"
   },
   {
     "EventName": "L2C_PRB_LSU",
     "EventCode": "0xBB",
-    "BriefDescription": "L2C probe LSU (for each core)",
-  },
-]
\ No newline at end of file
+    "BriefDescription": "L2C probe LSU (for each core)"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/floating_point.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/floating_point.json
index 0129715d3240..f35c788b28c7 100644
--- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/floating_point.json
+++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/floating_point.json
@@ -2,41 +2,41 @@
   {
     "EventName": "FPU0_UNCOMMIT_WAKEUP_BY_LOAD",
     "EventCode": "0x76",
-    "BriefDescription": "The oldest FPU0's instruction is woken up by load",
+    "BriefDescription": "The oldest FPU0's instruction is woken up by load"
   },
   {
     "EventName": "FPU0_UNCOMMIT_WAKEUP_BY_FX",
     "EventCode": "0x77",
-    "BriefDescription": "The oldest FPU0's instruction is woken up by INT",
+    "BriefDescription": "The oldest FPU0's instruction is woken up by INT"
   },
   {
     "EventName": "FPU0_UNCOMMIT_WAKEUP_BY_FP",
     "EventCode": "0x78",
-    "BriefDescription": "The oldest FPU0's instruction is woken up by FP",
+    "BriefDescription": "The oldest FPU0's instruction is woken up by FP"
   },
   {
     "EventName": "FPU1_UNCOMMIT_WAKEUP_BY_LOAD",
     "EventCode": "0x79",
-    "BriefDescription": "The oldest FPU1's instruction is wakeup by load",
+    "BriefDescription": "The oldest FPU1's instruction is wakeup by load"
   },
   {
     "EventName": "FPU1_UNCOMMIT_WAKEUP_BY_FX",
     "EventCode": "0x7A",
-    "BriefDescription": "The oldest FPU1's instruction is wakeup by INT",
+    "BriefDescription": "The oldest FPU1's instruction is wakeup by INT"
   },
   {
     "EventName": "FPU1_UNCOMMIT_WAKEUP_BY_FP",
     "EventCode": "0x7B",
-    "BriefDescription": "The oldest FPU1's instruction is wakeup by FP",
+    "BriefDescription": "The oldest FPU1's instruction is wakeup by FP"
   },
   {
     "EventName": "FPU0_COMMIT_WAIT",
     "EventCode": "0x7C",
-    "BriefDescription": "The total cycles of the oldest BasicBlock which is waiting for FPU0",
+    "BriefDescription": "The total cycles of the oldest BasicBlock which is waiting for FPU0"
   },
   {
     "EventName": "FPU1_COMMIT_WAIT",
     "EventCode": "0x7D",
-    "BriefDescription": "The total cycles of the oldest BasicBlock which is waiting for FPU1",
-  },
-]
\ No newline at end of file
+    "BriefDescription": "The total cycles of the oldest BasicBlock which is waiting for FPU1"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/instructions.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/instructions.json
index c37e0d1e467f..d5d57e8fcad9 100644
--- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/instructions.json
+++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/instructions.json
@@ -2,226 +2,226 @@
   {
     "EventName": "IFU_ROB_FLUSH",
     "EventCode": "0x1",
-    "BriefDescription": "ROB flush (all kinds of exceptions)",
+    "BriefDescription": "ROB flush (all kinds of exceptions)"
   },
   {
     "EventName": "IFU_BRU_FLUSH",
     "EventCode": "0x2",
-    "BriefDescription": "BRU flush (jump/branch instruction prediction miss)",
+    "BriefDescription": "BRU flush (jump/branch instruction prediction miss)"
   },
   {
     "EventName": "IFU_BPU_FLUSH",
     "EventCode": "0x3",
-    "BriefDescription": "BPU flush (mBTB prediction miss)",
+    "BriefDescription": "BPU flush (mBTB prediction miss)"
   },
   {
     "EventName": "IFU_MBTB_END_RET",
     "EventCode": "0x4",
-    "BriefDescription": "mBTB ending with return instruction",
+    "BriefDescription": "mBTB ending with return instruction"
   },
   {
     "EventName": "IFU_MBTB_END_BRTK",
     "EventCode": "0x5",
-    "BriefDescription": "mBTB ending with branch-tk instruction",
+    "BriefDescription": "mBTB ending with branch-tk instruction"
   },
   {
     "EventName": "IFU_MBTB_END_JUMP",
     "EventCode": "0x6",
-    "BriefDescription": "mBTB ending with other jump instruction",
+    "BriefDescription": "mBTB ending with other jump instruction"
   },
   {
     "EventName": "IFU_MBTB_END_SEQT",
     "EventCode": "0x7",
-    "BriefDescription": "mBTB ending with sequential (non-jump) instruction",
+    "BriefDescription": "mBTB ending with sequential (non-jump) instruction"
   },
   {
     "EventName": "IFU_MBTB_RET_MISS",
     "EventCode": "0x8",
-    "BriefDescription": "mBTB return instruction miss",
+    "BriefDescription": "mBTB return instruction miss"
   },
   {
     "EventName": "IFU_MBTB_BR_MISS",
     "EventCode": "0x9",
-    "BriefDescription": "mBTB branch instruction miss",
+    "BriefDescription": "mBTB branch instruction miss"
   },
   {
     "EventName": "IFU_MBTB_JUMP_MISS",
     "EventCode": "0xA",
-    "BriefDescription": "mBTB other jump instruction miss",
+    "BriefDescription": "mBTB other jump instruction miss"
   },
   {
     "EventName": "IFU_MBTB_SEQT_MISS",
     "EventCode": "0xB",
-    "BriefDescription": "mBTB sequential instruction miss",
+    "BriefDescription": "mBTB sequential instruction miss"
   },
   {
     "EventName": "IFU_L0BTB_HIT",
     "EventCode": "0xC",
-    "BriefDescription": "L0BTB hit",
+    "BriefDescription": "L0BTB hit"
   },
   {
     "EventName": "IFU_L1BTB_HIT",
     "EventCode": "0xD",
-    "BriefDescription": "L1BTB hit",
+    "BriefDescription": "L1BTB hit"
   },
   {
     "EventName": "IFU_MBTB_STALL",
     "EventCode": "0xE",
-    "BriefDescription": "mBTB stall",
+    "BriefDescription": "mBTB stall"
   },
   {
     "EventName": "IFU_IDLE",
     "EventCode": "0xF",
-    "BriefDescription": "IFU idle cycles wait for waking up ",
+    "BriefDescription": "IFU idle cycles wait for waking up "
   },
   {
     "EventName": "IFU_ITLB_MISS",
     "EventCode": "0x10",
-    "BriefDescription": "ITLB miss",
+    "BriefDescription": "ITLB miss"
   },
   {
     "EventName": "IFU_ITLB_STALL",
     "EventCode": "0x11",
-    "BriefDescription": "ITLB miss to stall cycles",
+    "BriefDescription": "ITLB miss to stall cycles"
   },
   {
     "EventName": "IFU_ITLB_ABORT",
     "EventCode": "0x12",
-    "BriefDescription": "ITLB miss abort (the flying request is flushed by the backend)",
+    "BriefDescription": "ITLB miss abort (the flying request is flushed by the backend)"
   },
   {
     "EventName": "IFU_ITLB_STALL_NULL",
     "EventCode": "0x13",
-    "BriefDescription": "ITLB miss to stall cycles when IFU has no instruction",
+    "BriefDescription": "ITLB miss to stall cycles when IFU has no instruction"
   },
   {
     "EventName": "IFU_FG_REQ",
     "EventCode": "0x14",
-    "BriefDescription": "Fetch-group access",
+    "BriefDescription": "Fetch-group access"
   },
   {
     "EventName": "IFU_FG_MISS",
     "EventCode": "0x15",
-    "BriefDescription": "Fetch-group miss",
+    "BriefDescription": "Fetch-group miss"
   },
   {
     "EventName": "IFU_ICACHE_STALL",
     "EventCode": "0x16",
-    "BriefDescription": "ICache miss to stall cycles",
+    "BriefDescription": "ICache miss to stall cycles"
   },
   {
     "EventName": "IFU_ICACHE_ABORT",
     "EventCode": "0x17",
-    "BriefDescription": "ICache miss abort (the flying request is flushed by backend)",
+    "BriefDescription": "ICache miss abort (the flying request is flushed by backend)"
   },
   {
     "EventName": "IFU_IPRED_REFILL",
     "EventCode": "0x18",
-    "BriefDescription": "IPrefetch refill",
+    "BriefDescription": "IPrefetch refill"
   },
   {
     "EventName": "IFU_IPRED_MISS",
     "EventCode": "0x19",
-    "BriefDescription": "IPrefetch miss",
+    "BriefDescription": "IPrefetch miss"
   },
   {
     "EventName": "IFU_ICACHE_MISS_NULL",
     "EventCode": "0x1A",
-    "BriefDescription": "ICache miss to stall cycles when IFU has no any instruction",
+    "BriefDescription": "ICache miss to stall cycles when IFU has no any instruction"
   },
   {
     "EventName": "IFU_BPU_BR_RETIRE",
     "EventCode": "0x1B",
-    "BriefDescription": "Condition branch instruction retire",
+    "BriefDescription": "Condition branch instruction retire"
   },
   {
     "EventName": "IFU_BPU_BR_MISS",
     "EventCode": "0x1C",
-    "BriefDescription": "Condition branch instruction miss",
+    "BriefDescription": "Condition branch instruction miss"
   },
   {
     "EventName": "IFU_BPU_RET_RETIRE",
     "EventCode": "0x1D",
-    "BriefDescription": "Return instruction retire",
+    "BriefDescription": "Return instruction retire"
   },
   {
     "EventName": "IFU_BPU_RET_MISS",
     "EventCode": "0x1E",
-    "BriefDescription": "Return instruction miss",
+    "BriefDescription": "Return instruction miss"
   },
   {
     "EventName": "IFU_BPU_IJR_RETIRE",
     "EventCode": "0x1F",
-    "BriefDescription": "Indirect JR instruction retire",
+    "BriefDescription": "Indirect JR instruction retire"
   },
   {
     "EventName": "IFU_BPU_IJR_MISS",
     "EventCode": "0x20",
-    "BriefDescription": "Indirect JR instruction miss (including without target)",
+    "BriefDescription": "Indirect JR instruction miss (including without target)"
   },
   {
     "EventName": "IFU_BPU_IJR_WOT",
     "EventCode": "0x21",
-    "BriefDescription": "Indirect JR instruction without target (IJTP miss)",
+    "BriefDescription": "Indirect JR instruction without target (IJTP miss)"
   },
   {
     "EventName": "IFU_IBUF_ISSUE",
     "EventCode": "0x22",
-    "BriefDescription": "IBUF valid while ID ready",
+    "BriefDescription": "IBUF valid while ID ready"
   },
   {
     "EventName": "IFU_IBUF_NORDY",
     "EventCode": "0x23",
-    "BriefDescription": "IBUF valid while ID not ready",
+    "BriefDescription": "IBUF valid while ID not ready"
   },
   {
     "EventName": "IFU_IBUF_NOVAL",
     "EventCode": "0x24",
-    "BriefDescription": "IBUF not valid while ID ready",
+    "BriefDescription": "IBUF not valid while ID ready"
   },
   {
     "EventName": "IFU_BB_1INSN_ISSUE",
     "EventCode": "0x25",
-    "BriefDescription": "IBUF issues 1 INSN in a BasicBlock",
+    "BriefDescription": "IBUF issues 1 INSN in a BasicBlock"
   },
   {
     "EventName": "IFU_BB_2INSN_ISSUE",
     "EventCode": "0x26",
-    "BriefDescription": "IBUF issues 2 INSN in a BasicBlock",
+    "BriefDescription": "IBUF issues 2 INSN in a BasicBlock"
   },
   {
     "EventName": "IFU_BB_3INSN_ISSUE",
     "EventCode": "0x27",
-    "BriefDescription": "IBUF issues 3 INSN in a BasicBlock",
+    "BriefDescription": "IBUF issues 3 INSN in a BasicBlock"
   },
   {
     "EventName": "IFU_BB_4INSN_ISSUE",
     "EventCode": "0x28",
-    "BriefDescription": "IBUF issues 4 INSN in a BasicBlock",
+    "BriefDescription": "IBUF issues 4 INSN in a BasicBlock"
   },
   {
     "EventName": "IFU_BB_5INSN_ISSUE",
     "EventCode": "0x29",
-    "BriefDescription": "IBUF issues 5 INSN in a BasicBlock",
+    "BriefDescription": "IBUF issues 5 INSN in a BasicBlock"
   },
   {
     "EventName": "IFU_BB_1INSN_FF_MT1",
     "EventCode": "0x2A",
-    "BriefDescription": "IBUF issues 1 INSN while IFIFO more than 1 insn  (>1)",
+    "BriefDescription": "IBUF issues 1 INSN while IFIFO more than 1 insn  (>1)"
   },
   {
     "EventName": "IFU_BB_2INSN_FF_MT2",
     "EventCode": "0x2B",
-    "BriefDescription": "IBUF issues 2 INSN while IFIFO more than 2 insn  (>2)",
+    "BriefDescription": "IBUF issues 2 INSN while IFIFO more than 2 insn  (>2)"
   },
   {
     "EventName": "IFU_BB_3INSB_FF_MT3",
     "EventCode": "0x2C",
-    "BriefDescription": "IBUF issues 3 INSN while IFIFO more than 3 insn  (>3)",
+    "BriefDescription": "IBUF issues 3 INSN while IFIFO more than 3 insn  (>3)"
   },
   {
     "EventName": "IFU_BB_4INSN_FF_MT4",
     "EventCode": "0x2D",
-    "BriefDescription": "IBUF issues 4 INSN while IFIFO more than 4 insn  (>4)",
-  },
-]
\ No newline at end of file
+    "BriefDescription": "IBUF issues 4 INSN while IFIFO more than 4 insn  (>4)"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/integer.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/integer.json
index c32c3429e84d..d66d45814ea2 100644
--- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/integer.json
+++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/integer.json
@@ -2,91 +2,91 @@
   {
     "EventName": "IU_INT_FREELIST_FULL",
     "EventCode": "0x4A",
-    "BriefDescription": "INT freelist full (not ready)",
+    "BriefDescription": "INT freelist full (not ready)"
   },
   {
     "EventName": "IU_FP_FREELIST_FULL",
     "EventCode": "0x4B",
-    "BriefDescription": "FP freelist full",
+    "BriefDescription": "FP freelist full"
   },
   {
     "EventName": "IU_VEC_FREELIST_FULL",
     "EventCode": "0x4C",
-    "BriefDescription": "VEC freelist full",
+    "BriefDescription": "VEC freelist full"
   },
   {
     "EventName": "IU_CHECKPOINT_FULL",
     "EventCode": "0x4D",
-    "BriefDescription": "The map-stack full",
+    "BriefDescription": "The map-stack full"
   },
   {
     "EventName": "IU_ROB_FULL",
     "EventCode": "0x4E",
-    "BriefDescription": "Reorder buffer full",
+    "BriefDescription": "Reorder buffer full"
   },
   {
     "EventName": "IU_ALU_RSV_FULL",
     "EventCode": "0x4F",
-    "BriefDescription": "ALU reservation station full",
+    "BriefDescription": "ALU reservation station full"
   },
   {
     "EventName": "IU_BR_RSV_FULL",
     "EventCode": "0x50",
-    "BriefDescription": "BR reservation station full",
+    "BriefDescription": "BR reservation station full"
   },
   {
     "EventName": "IU_MDIV_RSV_FULL",
     "EventCode": "0x51",
-    "BriefDescription": "MDIV reservation station full",
+    "BriefDescription": "MDIV reservation station full"
   },
   {
     "EventName": "IU_LSU_RSV_FULL",
     "EventCode": "0x52",
-    "BriefDescription": "LSU reservation station full",
+    "BriefDescription": "LSU reservation station full"
   },
   {
     "EventName": "IU_FP_RSV_FULL",
     "EventCode": "0x53",
-    "BriefDescription": "FP reservation station full",
+    "BriefDescription": "FP reservation station full"
   },
   {
     "EventName": "IU_VEC_RST_FULL",
     "EventCode": "0x54",
-    "BriefDescription": "VEC reservation station full",
+    "BriefDescription": "VEC reservation station full"
   },
   {
     "EventName": "IU_LDQ_FULL",
     "EventCode": "0x55",
-    "BriefDescription": "LSU LDQ full",
+    "BriefDescription": "LSU LDQ full"
   },
   {
     "EventName": "IU_STQ_FULL",
     "EventCode": "0x56",
-    "BriefDescription": "LSU STQ full",
+    "BriefDescription": "LSU STQ full"
   },
   {
     "EventName": "IFU_BB_5INSN_ISSUE",
     "EventCode": "0x57",
-    "BriefDescription": "ROB commits pdead BasicBlock with exception",
+    "BriefDescription": "ROB commits pdead BasicBlock with exception"
   },
   {
     "EventName": "IU_COMMIT_SINGLE_VAL",
     "EventCode": "0x58",
-    "BriefDescription": "ROB commits only one valid BasicBlock at the cycle",
+    "BriefDescription": "ROB commits only one valid BasicBlock at the cycle"
   },
   {
     "EventName": "IU_COMMIT_DOUBLE_VAL",
     "EventCode": "0x59",
-    "BriefDescription": "ROB commits two valid BasicBlock at the cycle",
+    "BriefDescription": "ROB commits two valid BasicBlock at the cycle"
   },
   {
     "EventName": "IU_COMMIT_PAGEFAULT",
     "EventCode": "0x5A",
-    "BriefDescription": "ROB commits a pagefault exception",
+    "BriefDescription": "ROB commits a pagefault exception"
   },
   {
     "EventName": "IU_UNCOMMIT",
     "EventCode": "0x5B",
-    "BriefDescription": "ROB can't commit BasicBlock because of unfinished instruction",
-  },
-]
\ No newline at end of file
+    "BriefDescription": "ROB can't commit BasicBlock because of unfinished instruction"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/load_store.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/load_store.json
index ad5114092299..a31f790a8a59 100644
--- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/load_store.json
+++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/load_store.json
@@ -2,181 +2,181 @@
   {
     "EventName": "LSU_C_LD_NUM",
     "EventCode": "0x86",
-    "BriefDescription": "Cacheable load instruction",
+    "BriefDescription": "Cacheable load instruction"
   },
   {
     "EventName": "LSU_LD_REPLAY_NUM",
     "EventCode": "0x87",
-    "BriefDescription": "Load instruction replay",
+    "BriefDescription": "Load instruction replay"
   },
   {
     "EventName": "LSU_C_ST_NUM",
     "EventCode": "0x88",
-    "BriefDescription": "Cacheable store instruction",
+    "BriefDescription": "Cacheable store instruction"
   },
   {
     "EventName": "LSU_ST_ALLOC_MB_FULL_NUM",
     "EventCode": "0x89",
-    "BriefDescription": "Cacheable store allocates MB but MB (merge buffer) is full",
+    "BriefDescription": "Cacheable store allocates MB but MB (merge buffer) is full"
   },
   {
     "EventName": "LSU_NC_ST_ALLOC_WCB_FULL_NUM",
     "EventCode": "0x8A",
-    "BriefDescription": "Uncacheable store allocates WCB (Write Combination Buffer) but WCB is full.",
+    "BriefDescription": "Uncacheable store allocates WCB (Write Combination Buffer) but WCB is full."
   },
   {
     "EventName": "LSU_ST_HAS_PA_NO_DAT_NUM",
     "EventCode": "0x8B",
-    "BriefDescription": "Store instruction get PA but no data",
+    "BriefDescription": "Store instruction get PA but no data"
   },
   {
     "EventName": "LSU_BP_DAT_ALU_NUM",
     "EventCode": "0x8C",
-    "BriefDescription": "Bypass data from ALU",
+    "BriefDescription": "Bypass data from ALU"
   },
   {
     "EventName": "LSU_BP_DAT_BRU_NUM",
     "EventCode": "0x8D",
-    "BriefDescription": "Bypass data from BRU",
+    "BriefDescription": "Bypass data from BRU"
   },
   {
     "EventName": "LSU_BP_DAT_MDIV_NUM",
     "EventCode": "0x8E",
-    "BriefDescription": "Bypass data from MDIV",
+    "BriefDescription": "Bypass data from MDIV"
   },
   {
     "EventName": "LSU_BP_DAT_FPU_NUM",
     "EventCode": "0x8F",
-    "BriefDescription": "Bypass data from FPU",
+    "BriefDescription": "Bypass data from FPU"
   },
   {
     "EventName": "LSU_BP_DAT_VEC_NUM",
     "EventCode": "0x90",
-    "BriefDescription": "Bypass data from VEC",
+    "BriefDescription": "Bypass data from VEC"
   },
   {
     "EventName": "LSU_BP_DAT_LSU_NUM",
     "EventCode": "0x91",
-    "BriefDescription": "Bypass data from LSU",
+    "BriefDescription": "Bypass data from LSU"
   },
   {
     "EventName": "LSU_BP_DAT_LSU_MISPREDICT_NUM",
     "EventCode": "0x92",
-    "BriefDescription": "Load wakeup by release but mispredict",
+    "BriefDescription": "Load wakeup by release but mispredict"
   },
   {
     "EventName": "LSU_LD_REQ_L1D_NUM",
     "EventCode": "0x93",
-    "BriefDescription": "Load request DCache",
+    "BriefDescription": "Load request DCache"
   },
   {
     "EventName": "LSU_LD_MISS_L1D_NUM",
     "EventCode": "0x94",
-    "BriefDescription": "Load miss DCache",
+    "BriefDescription": "Load miss DCache"
   },
   {
     "EventName": "LSU_LD_MISS_L1D_EVICT_PF_N UM",
     "EventCode": "0x95",
-    "BriefDescription": "Load misses in DCache and the cache line is evicted by the prefetcher",
+    "BriefDescription": "Load misses in DCache and the cache line is evicted by the prefetcher"
   },
   {
     "EventName": "LSU_LD_HIT_L1D_NUM",
     "EventCode": "0x96",
-    "BriefDescription": "Load hit DCache",
+    "BriefDescription": "Load hit DCache"
   },
   {
     "EventName": "LSU_LD_HIT_L1D_PF_NUM",
     "EventCode": "0x97",
-    "BriefDescription": "Load hit DCache and the cache line is prefetch",
+    "BriefDescription": "Load hit DCache and the cache line is prefetch"
   },
   {
     "EventName": "LSU_PF_REQ_L2C_NUM",
     "EventCode": "0x98",
-    "BriefDescription": "Prefetcher request L2C",
+    "BriefDescription": "Prefetcher request L2C"
   },
   {
     "EventName": "LSU_ST_REQ_L1D_NUM",
     "EventCode": "0x99",
-    "BriefDescription": "Store request DCache",
+    "BriefDescription": "Store request DCache"
   },
   {
     "EventName": "LSU_ST_MISS_L1D_NUM",
     "EventCode": "0x9A",
-    "BriefDescription": "Store miss DCache",
+    "BriefDescription": "Store miss DCache"
   },
   {
     "EventName": "LSU_ST_HIT_L1D_NUM",
     "EventCode": "0x9B",
-    "BriefDescription": "Store hit DCache",
+    "BriefDescription": "Store hit DCache"
   },
   {
     "EventName": "LSU_ST_HIT_L1D_SN_NUM",
     "EventCode": "0x9C",
-    "BriefDescription": "Store hit DCache MESI is S state",
+    "BriefDescription": "Store hit DCache MESI is S state"
   },
   {
     "EventName": "LSU_LD_ALLOC_MQ_FULL_NUM",
     "EventCode": "0x9D",
-    "BriefDescription": "Load allocate MISSQ but MISSQ is full",
+    "BriefDescription": "Load allocate MISSQ but MISSQ is full"
   },
   {
     "EventName": "LSU_LD_ALLOC_MQ_WAYLOCK_NUM",
     "EventCode": "0x9E",
-    "BriefDescription": "Load allocate MISSQ meet way-lock",
+    "BriefDescription": "Load allocate MISSQ meet way-lock"
   },
   {
     "EventName": "LSU_DTLB_REQ",
     "EventCode": "0x9F",
-    "BriefDescription": "Request DTLB",
+    "BriefDescription": "Request DTLB"
   },
   {
     "EventName": "LSU_DTLB_MISS",
     "EventCode": "0xA0",
-    "BriefDescription": "Miss DTLB",
+    "BriefDescription": "Miss DTLB"
   },
   {
     "EventName": "LSU_SLOT_REQ",
     "EventCode": "0xA1",
-    "BriefDescription": "DTLB miss to request MMU",
+    "BriefDescription": "DTLB miss to request MMU"
   },
   {
     "EventName": "LSU_SLOT_STALL",
     "EventCode": "0xA2",
-    "BriefDescription": "DTLB request MMU cycles",
+    "BriefDescription": "DTLB request MMU cycles"
   },
   {
     "EventName": "LSU_SLOT_ABORT",
     "EventCode": "0xA3",
-    "BriefDescription": "DTLB flying miss is abort",
+    "BriefDescription": "DTLB flying miss is abort"
   },
   {
     "EventName": "LSU_RV_EMPTY",
     "EventCode": "0xA4",
-    "BriefDescription": "RV empty when allocate and source data is ready (can bypass)",
+    "BriefDescription": "RV empty when allocate and source data is ready (can bypass)"
   },
   {
     "EventName": "LSU_LD_BP_LD_NUM",
     "EventCode": "0xA5",
-    "BriefDescription": "Load bypass load",
+    "BriefDescription": "Load bypass load"
   },
   {
     "EventName": "LSU_LD_BP_ST_NUM",
     "EventCode": "0xA6",
-    "BriefDescription": "Load bypass store",
+    "BriefDescription": "Load bypass store"
   },
   {
     "EventName": "LSU_NUKE_LD_LD_NUM",
     "EventCode": "0xA7",
-    "BriefDescription": "Load bypass load cause nuke flush",
+    "BriefDescription": "Load bypass load cause nuke flush"
   },
   {
     "EventName": "LSU_NUKE_LD_ST_NUM",
     "EventCode": "0xA8",
-    "BriefDescription": "Load bypass store cause nuke flush",
+    "BriefDescription": "Load bypass store cause nuke flush"
   },
   {
     "EventName": "LSU_LD_HIT_MDB_NUM",
     "EventCode": "0xA9",
-    "BriefDescription": "Load hit MDB (Memory Disambiguation Buffer)",
-  },
-]
\ No newline at end of file
+    "BriefDescription": "Load hit MDB (Memory Disambiguation Buffer)"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/memory.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/memory.json
index 65f9a9cd62c5..59a18ad385ee 100644
--- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/memory.json
+++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/memory.json
@@ -2,61 +2,61 @@
   {
     "EventName": "MMU_IFU_REQ",
     "EventCode": "0x36",
-    "BriefDescription": "ITLB miss to access MMU TLBs",
+    "BriefDescription": "ITLB miss to access MMU TLBs"
   },
   {
     "EventName": "MMU_IFU_MISS",
     "EventCode": "0x37",
-    "BriefDescription": "ITLB miss to access MMU TLBs, which also miss",
+    "BriefDescription": "ITLB miss to access MMU TLBs, which also miss"
   },
   {
     "EventName": "MMU_LSU_REQ",
     "EventCode": "0x38",
-    "BriefDescription": "DTLB miss to access MMU TLBs",
+    "BriefDescription": "DTLB miss to access MMU TLBs"
   },
   {
     "EventName": "MMU_LSU_MISS",
     "EventCode": "0x39",
-    "BriefDescription": "DTLB miss to access MMU TLBs, which also miss",
+    "BriefDescription": "DTLB miss to access MMU TLBs, which also miss"
   },
   {
     "EventName": "MMU_IFU_PTEC_REQ",
     "EventCode": "0x3A",
-    "BriefDescription": "ITLB miss to walk PTW then access PTE-Cache",
+    "BriefDescription": "ITLB miss to walk PTW then access PTE-Cache"
   },
   {
     "EventName": "MMU_IFU_PTEC_HIT",
     "EventCode": "0x3B",
-    "BriefDescription": "ITLB miss to walk PTW then hit PTE-Cache",
+    "BriefDescription": "ITLB miss to walk PTW then hit PTE-Cache"
   },
   {
     "EventName": "MMU_IFU_L2C_REQ",
     "EventCode": "0x3C",
-    "BriefDescription": "ITLB miss to walk PTW then request L2C",
+    "BriefDescription": "ITLB miss to walk PTW then request L2C"
   },
   {
     "EventName": "MMU_IFU_L2C_WAIT",
     "EventCode": "0x3D",
-    "BriefDescription": "ITLB miss to walk PTW then wait for L2C to stall cycles",
+    "BriefDescription": "ITLB miss to walk PTW then wait for L2C to stall cycles"
   },
   {
     "EventName": "MMU_LSU_PTEC_REQ",
     "EventCode": "0x3E",
-    "BriefDescription": "DTLB miss to walk PTW and then access PTE-Cache",
+    "BriefDescription": "DTLB miss to walk PTW and then access PTE-Cache"
   },
   {
     "EventName": "MMU_LSU_PTEC_HIT",
     "EventCode": "0x3F",
-    "BriefDescription": "DTLB miss to walk PTW and then hit PTE-Cache",
+    "BriefDescription": "DTLB miss to walk PTW and then hit PTE-Cache"
   },
   {
     "EventName": "MMU_LSU_L2C_REQ",
     "EventCode": "0x40",
-    "BriefDescription": "DTLB miss to walk PTW and then request L2C",
+    "BriefDescription": "DTLB miss to walk PTW and then request L2C"
   },
   {
     "EventName": "MMU_LSU_L2C_WAIT",
     "EventCode": "0x41",
-    "BriefDescription": "DTLB miss to walk PTW and then wait for L2C to stall cycles",
-  },
-]
\ No newline at end of file
+    "BriefDescription": "DTLB miss to walk PTW and then wait for L2C to stall cycles"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/multiply_div.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/multiply_div.json
index af3ae8e56035..c1aac0a28170 100644
--- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/multiply_div.json
+++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/multiply_div.json
@@ -2,51 +2,51 @@
   {
     "EventName": "MDIV_DIV_INSTR",
     "EventCode": "0x64",
-    "BriefDescription": "Divide instruction number",
+    "BriefDescription": "Divide instruction number"
   },
   {
     "EventName": "MDIV_WAKEUP_BY_LOAD",
     "EventCode": "0x65",
-    "BriefDescription": "Wakeup by load instruction",
+    "BriefDescription": "Wakeup by load instruction"
   },
   {
     "EventName": "MDIV_WAKEUP_BY_FP",
     "EventCode": "0x66",
-    "BriefDescription": "Wakeup by FP instruction",
+    "BriefDescription": "Wakeup by FP instruction"
   },
   {
     "EventName": "MDIV_WAKEUP_BY_FX",
     "EventCode": "0x67",
-    "BriefDescription": "Wakeup by INT instruction",
+    "BriefDescription": "Wakeup by INT instruction"
   },
   {
     "EventName": "MDIV_DIV_BUSY",
     "EventCode": "0x68",
-    "BriefDescription": "The total cycles of divide instruction execution",
+    "BriefDescription": "The total cycles of divide instruction execution"
   },
   {
     "EventName": "MDIV_EARLY_EXIT",
     "EventCode": "0x69",
-    "BriefDescription": "Divide instructions finished ahead of time",
+    "BriefDescription": "Divide instructions finished ahead of time"
   },
   {
     "EventName": "MDIV_COMMIT_WAIT",
     "EventCode": "0x6A",
-    "BriefDescription": "The total cycles of the oldest basic block which is waiting for MDIV",
+    "BriefDescription": "The total cycles of the oldest basic block which is waiting for MDIV"
   },
   {
     "EventName": "MDIV_UNCOMMIT_WAKEUP_BY_LOAD",
     "EventCode": "0x6B",
-    "BriefDescription": "The oldest MDIV's instruction is woken up by load",
+    "BriefDescription": "The oldest MDIV's instruction is woken up by load"
   },
   {
     "EventName": "MDIV_UNCOMMIT_WAKEUP_BY_FX",
     "EventCode": "0x6C",
-    "BriefDescription": "The oldest MDIV's instruction is woken up by INT",
+    "BriefDescription": "The oldest MDIV's instruction is woken up by INT"
   },
   {
     "EventName": "MDIV_UNCOMMIT_WAKEUP_BY_FP",
     "EventCode": "0x6D",
-    "BriefDescription": "The oldest MDIV's instruction is woken up by FP",
-  },
-]
\ No newline at end of file
+    "BriefDescription": "The oldest MDIV's instruction is woken up by FP"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/vector.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/vector.json
index 01cbda72f197..ee4889465938 100644
--- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe/vector.json
+++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe/vector.json
@@ -2,116 +2,116 @@
   {
     "EventName": "VEC_LD_CL_MFULL",
     "EventCode": "0xC4",
-    "BriefDescription": "load cache-line manager full",
+    "BriefDescription": "load cache-line manager full"
   },
   {
     "EventName": "VEC_LD_CL_MREP_VA2PA_ARB",
     "EventCode": "0xC5",
-    "BriefDescription": "load cache-line manager replay due to VA2PA arbitration",
+    "BriefDescription": "load cache-line manager replay due to VA2PA arbitration"
   },
   {
     "EventName": "VEC_LD_CL_MREP_VDCACHE_ARB",
     "EventCode": "0xC6",
-    "BriefDescription": "load cache-line manager replay due to VDCache arbitration",
+    "BriefDescription": "load cache-line manager replay due to VDCache arbitration"
   },
   {
     "EventName": "VEC_LD_QFULL",
     "EventCode": "0xC7",
-    "BriefDescription": "load queue full",
+    "BriefDescription": "load queue full"
   },
   {
     "EventName": "VEC_ST_CL_MFULL",
     "EventCode": "0xC8",
-    "BriefDescription": "store cache-line manager full",
+    "BriefDescription": "store cache-line manager full"
   },
   {
     "EventName": "VEC_ST_CL_MREP_VA2PA_ARB",
     "EventCode": "0xC9",
-    "BriefDescription": "store cache-line manager replay due to VA2PA arbitration",
+    "BriefDescription": "store cache-line manager replay due to VA2PA arbitration"
   },
   {
     "EventName": "VEC_ST_WAIT_CMT_NOT_OLDEST",
     "EventCode": "0xCA",
-    "BriefDescription": "store wait to commit due to not oldest",
+    "BriefDescription": "store wait to commit due to not oldest"
   },
   {
     "EventName": "VEC_LD_ALLOC_MISS_QFAIL_FULL",
     "EventCode": "0xCB",
-    "BriefDescription": "load allocate miss queue fail due to full",
+    "BriefDescription": "load allocate miss queue fail due to full"
   },
   {
     "EventName": "VEC_ST_ALLOC_MERGE_BUFF_FAIL_FULL",
     "EventCode": "0xCC",
-    "BriefDescription": "store allocates merge buffer fail due to full",
+    "BriefDescription": "store allocates merge buffer fail due to full"
   },
   {
     "EventName": "VEC_LD_VDCACHE",
     "EventCode": "0xCD",
-    "BriefDescription": "load access VDCache",
+    "BriefDescription": "load access VDCache"
   },
   {
     "EventName": "VEC_LD_MISS_VDCACHE",
     "EventCode": "0xCE",
-    "BriefDescription": "load miss VDCache",
+    "BriefDescription": "load miss VDCache"
   },
   {
     "EventName": "VEC_COM_IRV_STALL",
     "EventCode": "0xCF",
-    "BriefDescription": "computing instruction RV stall",
+    "BriefDescription": "computing instruction RV stall"
   },
   {
     "EventName": "VEC_COM_IRV_STALL_VECTAG",
     "EventCode": "0xD0",
-    "BriefDescription": "computing instruction RV stall due to vectag",
+    "BriefDescription": "computing instruction RV stall due to vectag"
   },
   {
     "EventName": "VEC_COM_IRV_STALL_REGBUSY_FULL",
     "EventCode": "0xD1",
-    "BriefDescription": "computing instruction RV stall due to REGBUSY full",
+    "BriefDescription": "computing instruction RV stall due to REGBUSY full"
   },
   {
     "EventName": "VEC_COM_IRV_E1_STALL_WAW_WAR",
     "EventCode": "0xD2",
-    "BriefDescription": "computing instruction RV's entry1 stall due to WAW or WAR hazard",
+    "BriefDescription": "computing instruction RV's entry1 stall due to WAW or WAR hazard"
   },
   {
     "EventName": "VEC_COM_IRV_E1_READY_E0_NREADY",
     "EventCode": "0xD3",
-    "BriefDescription": "computing instruction RV's entry1 ready while entry0 not ready",
+    "BriefDescription": "computing instruction RV's entry1 ready while entry0 not ready"
   },
   {
     "EventName": "VEC_COM_IRV_E0_STALL_WAIT_LD_DATA",
     "EventCode": "0xD4",
-    "BriefDescription": "computing instruction RV's entry 0 stall due to wait load's data",
+    "BriefDescription": "computing instruction RV's entry 0 stall due to wait load's data"
   },
   {
     "EventName": "VEC_COM_IRV_E0_STALL_PREV_COM_INST",
     "EventCode": "0xD5",
-    "BriefDescription": "computing instruction RV's entry 0 stall due to wait previous computing instruction's result",
+    "BriefDescription": "computing instruction RV's entry 0 stall due to wait previous computing instruction's result"
   },
   {
     "EventName": "VEC_LD_ST_IRV_STALL",
     "EventCode": "0xD6",
-    "BriefDescription": "load/store instruction RV's stall",
+    "BriefDescription": "load/store instruction RV's stall"
   },
   {
     "EventName": "VEC_LD_ST_IRV_STALL_VECTAG",
     "EventCode": "0xD7",
-    "BriefDescription": "load/store instruction RV's stall due to vectag",
+    "BriefDescription": "load/store instruction RV's stall due to vectag"
   },
   {
     "EventName": "VEC_LD_ST_IRV_STALL_REGBUSY_FULL",
     "EventCode": "0xD8",
-    "BriefDescription": "load/store instruction RV's stall due to REGBUSY full",
+    "BriefDescription": "load/store instruction RV's stall due to REGBUSY full"
   },
   {
     "EventName": "VEC_LD_ST_IRV_E1_STALL_WAW_WAR",
     "EventCode": "0xD9",
-    "BriefDescription": "load/store instruction RV's entry1 stall due to WAW or WAR hazard",
+    "BriefDescription": "load/store instruction RV's entry1 stall due to WAW or WAR hazard"
   },
   {
     "EventName": "VEC_LD_ST_IRV_E1_READY_E0_NREADY",
     "EventCode": "0xDA",
-    "BriefDescription": "load/store instruction RV's entry1 ready while entry0 not ready",
-  },
-]
\ No newline at end of file
+    "BriefDescription": "load/store instruction RV's entry1 ready while entry0 not ready"
+  }
+]