riscv: dts: starfive: dubhe: Move fpga common to *common.dtsi

Move Dubhe FPGA common DT to *common.dtsi file, in preparation for Dubhe 80.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>

2 files changed, 112 insertions, 109 deletions

diff --git a/arch/riscv/boot/dts/starfive/dubhe90_fpga.dts b/arch/riscv/boot/dts/starfive/dubhe90_fpga.dts
index d18aebd140fe..5f9f266165e6 100644
--- a/arch/riscv/boot/dts/starfive/dubhe90_fpga.dts
+++ b/arch/riscv/boot/dts/starfive/dubhe90_fpga.dts
@@ -2,112 +2,4 @@
 /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
 
 #include "dubhe90.dtsi"
-
-/ {
-	model = "StarFive Dubhe FPGA";
-
-	aliases {
-		ethernet0 = &gmac0;
-		serial0 = &uart0;
-	};
-
-	chosen {
-		bootargs = "console=ttySIF0,115200 earlycon=sbi ip=:::255.255.255.0::eth0:dhcp";
-	};
-
-	cpus {
-		timebase-frequency = <25000000>;
-
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0x2 0x0>;
-	};
-
-	soc {
-
-		fpga_2p5mhz_clk: fpga_2p5mhz_clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <2500000>;
-		};
-
-		fpga_50mhz_clk: fpga_50mhz_clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <50000000>;
-		};
-	};
-};
-
-&gmac0 {
-	status = "okay";
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethernet_phy0>;
-	clocks = <&fpga_2p5mhz_clk>,
-		 <&fpga_2p5mhz_clk>,
-		 <&fpga_2p5mhz_clk>,
-		 <&fpga_50mhz_clk>,
-		 <&fpga_50mhz_clk>,
-		 <&fpga_2p5mhz_clk>;
-
-	mdio0 {
-		compatible = "snps,dwmac-mdio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		ethernet_phy0: ethernet-phy@0 {
-			reg = <0>;
-			max-speed = <10>;
-			device_type = "ethernet-phy";
-			marvell,reg-init =
-				<0x0 0x4 0 0x0441>, /*Page 0, Reg 4 <- 0x0441*/
-				<0x12 0x14 0 0x0>, /*Page 18, Reg 20 <- 0x0*/
-				<0x0 0x0 0 0x1100>; /*Page 0, Reg 0 <- 0x1100*/
-		};
-	};
-};
-
-&spi0 {
-	status = "okay";
-	mmc@0 {
-		compatible = "mmc-spi-slot";
-		reg = <0>;
-		spi-max-frequency = <20000000>;
-		voltage-ranges = <3300 3300>;
-		disable-wp;
-	};
-};
-
-&qspi1 {
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <20000000>;
-		m25p,fast-read;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <1>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				reg = <0x000000 0x2000000>;
-				label = "Boot images";
-			};
-
-			partition@2000000 {
-				reg = <0x2000000 0x6000000>;
-				label = "Rootfs";
-			};
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
+#include "dubhe_fpga_common.dtsi"
diff --git a/arch/riscv/boot/dts/starfive/dubhe_fpga_common.dtsi b/arch/riscv/boot/dts/starfive/dubhe_fpga_common.dtsi
new file mode 100644
index 000000000000..b310a1faf661
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/dubhe_fpga_common.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
+
+/ {
+	model = "StarFive Dubhe FPGA";
+
+	aliases {
+		ethernet0 = &gmac0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		bootargs = "console=ttySIF0,115200 earlycon=sbi ip=:::255.255.255.0::eth0:dhcp";
+	};
+
+	cpus {
+		timebase-frequency = <25000000>;
+
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x0>;
+	};
+
+	soc {
+
+		fpga_2p5mhz_clk: fpga_2p5mhz_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <2500000>;
+		};
+
+		fpga_50mhz_clk: fpga_50mhz_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy0>;
+	clocks = <&fpga_2p5mhz_clk>,
+		 <&fpga_2p5mhz_clk>,
+		 <&fpga_2p5mhz_clk>,
+		 <&fpga_50mhz_clk>,
+		 <&fpga_50mhz_clk>,
+		 <&fpga_2p5mhz_clk>;
+
+	mdio0 {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ethernet_phy0: ethernet-phy@0 {
+			reg = <0>;
+			max-speed = <10>;
+			device_type = "ethernet-phy";
+			marvell,reg-init =
+				<0x0 0x4 0 0x0441>, /*Page 0, Reg 4 <- 0x0441*/
+				<0x12 0x14 0 0x0>, /*Page 18, Reg 20 <- 0x0*/
+				<0x0 0x0 0 0x1100>; /*Page 0, Reg 0 <- 0x1100*/
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+	mmc@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		voltage-ranges = <3300 3300>;
+		disable-wp;
+	};
+};
+
+&qspi1 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		m25p,fast-read;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x000000 0x2000000>;
+				label = "Boot images";
+			};
+
+			partition@2000000 {
+				reg = <0x2000000 0x6000000>;
+				label = "Rootfs";
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};