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authorPeng Fan <peng.fan@nxp.com>2022-09-06 06:28:13 +0300
committerShawn Guo <shawnguo@kernel.org>2022-09-17 11:25:50 +0300
commit121494030c533a9e390ba82b370619d1e0bad7a1 (patch)
tree51619d4efc5d2ba2b60ce293b92abfde122a794f
parent4fed4d20c59b338d9f5ce3dd11820d09ed4e8546 (diff)
downloadlinux-121494030c533a9e390ba82b370619d1e0bad7a1.tar.xz
dt-bindings: soc: add i.MX93 mediamix blk ctrl
Add DT bindings for i.MX93 MEDIAMIX BLK CTRL. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml80
-rw-r--r--include/dt-bindings/power/fsl,imx93-power.h15
2 files changed, 95 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
new file mode 100644
index 000000000000..792ebecec22d
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-media-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX93 Media blk-ctrl
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+description:
+ The i.MX93 MEDIAMIX domain contains control and status registers known
+ as MEDIAMIX Block Control (MEDIAMIX BLK_CTRL). These registers include
+ clocking, reset, and miscellaneous top-level controls for peripherals
+ within the MEDIAMIX domain
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx93-media-blk-ctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ maxItems: 10
+
+ clock-names:
+ items:
+ - const: apb
+ - const: axi
+ - const: nic
+ - const: disp
+ - const: cam
+ - const: pxp
+ - const: lcdif
+ - const: isi
+ - const: csi
+ - const: dsi
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx93-clock.h>
+ #include <dt-bindings/power/fsl,imx93-power.h>
+
+ media_blk_ctrl: system-controller@4ac10000 {
+ compatible = "fsl,imx93-media-blk-ctrl", "syscon";
+ reg = <0x4ac10000 0x10000>;
+ power-domains = <&mediamix>;
+ clocks = <&clk IMX93_CLK_MEDIA_APB>,
+ <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_NIC_MEDIA_GATE>,
+ <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+ <&clk IMX93_CLK_CAM_PIX>,
+ <&clk IMX93_CLK_PXP_GATE>,
+ <&clk IMX93_CLK_LCDIF_GATE>,
+ <&clk IMX93_CLK_ISI_GATE>,
+ <&clk IMX93_CLK_MIPI_CSI_GATE>,
+ <&clk IMX93_CLK_MIPI_DSI_GATE>;
+ clock-names = "apb", "axi", "nic", "disp", "cam",
+ "pxp", "lcdif", "isi", "csi", "dsi";
+ #power-domain-cells = <1>;
+ };
diff --git a/include/dt-bindings/power/fsl,imx93-power.h b/include/dt-bindings/power/fsl,imx93-power.h
new file mode 100644
index 000000000000..17f9f015bf7d
--- /dev/null
+++ b/include/dt-bindings/power/fsl,imx93-power.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __DT_BINDINGS_IMX93_POWER_H__
+#define __DT_BINDINGS_IMX93_POWER_H__
+
+#define IMX93_MEDIABLK_PD_MIPI_DSI 0
+#define IMX93_MEDIABLK_PD_MIPI_CSI 1
+#define IMX93_MEDIABLK_PD_PXP 2
+#define IMX93_MEDIABLK_PD_LCDIF 3
+#define IMX93_MEDIABLK_PD_ISI 4
+
+#endif