diff options
author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2018-07-06 18:52:59 +0300 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-07-07 18:00:51 +0300 |
commit | 3ff10703c74ab08d4861b0d3924dc3a3f05da004 (patch) | |
tree | 11bccacc8c6d75c535ebb62faab7dacc8c7fb8f7 | |
parent | 447735fafe5f8779f07091f5d30cca6a44c0c1fd (diff) | |
download | linux-3ff10703c74ab08d4861b0d3924dc3a3f05da004.tar.xz |
serial: 8250_dw: Introduce IO accessors to extended registers
There are several extended (in comparison to the traditional 16550)
registers are present in Synopsys DesignWare UART. All of them
are 32-bit ones.
Introduce helpers to simplify access to them and convert existing users.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r-- | drivers/tty/serial/8250/8250_dw.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index aff04f1de3a5..fa8a00e8c9c6 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -67,6 +67,21 @@ struct dw8250_data { unsigned int uart_16550_compatible:1; }; +static inline u32 dw8250_readl_ext(struct uart_port *p, int offset) +{ + if (p->iotype == UPIO_MEM32BE) + return ioread32be(p->membase + offset); + return readl(p->membase + offset); +} + +static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) +{ + if (p->iotype == UPIO_MEM32BE) + iowrite32be(reg, p->membase + offset); + else + writel(reg, p->membase + offset); +} + static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) { struct dw8250_data *d = p->private_data; @@ -404,20 +419,14 @@ static void dw8250_setup_port(struct uart_port *p) * If the Component Version Register returns zero, we know that * ADDITIONAL_FEATURES are not enabled. No need to go any further. */ - if (p->iotype == UPIO_MEM32BE) - reg = ioread32be(p->membase + DW_UART_UCV); - else - reg = readl(p->membase + DW_UART_UCV); + reg = dw8250_readl_ext(p, DW_UART_UCV); if (!reg) return; dev_dbg(p->dev, "Designware UART version %c.%c%c\n", (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); - if (p->iotype == UPIO_MEM32BE) - reg = ioread32be(p->membase + DW_UART_CPR); - else - reg = readl(p->membase + DW_UART_CPR); + reg = dw8250_readl_ext(p, DW_UART_CPR); if (!reg) return; |