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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-03-14 03:30:05 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:29:54 +0300 |
| commit | 4688d9ce2e3d0ad59147970295018cec4c67afa5 (patch) | |
| tree | bd8d078af411c997ecd90e5ac5fa73978b7183ec | |
| parent | a19220fa5f1a740d98654ee1d6cf11a8e0158018 (diff) | |
| download | linux-4688d9ce2e3d0ad59147970295018cec4c67afa5.tar.xz | |
drm/xe: Add PVC engine workarounds
Sync PVC engine workarounds with i915.
v2: Remove 16016694945. It was added by mistake. It's a GT workaround,
already present in the GT table (Matt Roper)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230314003012.2600353-8-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa.c | 22 |
2 files changed, 31 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 411cdbae1894..e55c2f83b353 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -43,6 +43,9 @@ #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) +#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) +#define PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15) + #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) @@ -230,6 +233,9 @@ #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) +#define CACHE_MODE_SS MCR_REG(0xe420) +#define DISABLE_ECC REG_BIT(5) + #define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c) #define GEN12_DISABLE_GRF_CLEAR REG_BIT(13) #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) @@ -246,6 +252,9 @@ #define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) #define GEN12_DISABLE_DOP_GATING REG_BIT(0) +#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) +#define DISABLE_D8_D16_COASLESCE REG_BIT(30) + #define SARB_CHICKEN1 MCR_REG(0xe90c) #define COMP_CKN_IN REG_GENMASK(30, 29) diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index e8d523033b87..4fe01168f45f 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -276,6 +276,28 @@ static const struct xe_rtp_entry engine_was[] = { XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, + + /* PVC */ + + { XE_RTP_NAME("22014226127"), + XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) + }, + { XE_RTP_NAME("14015227452"), + XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), + XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE, + XE_RTP_ACTION_FLAG(MASKED_REG))) + }, + { XE_RTP_NAME("16015675438"), + XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), + XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2, PERF_FIX_BALANCING_CFE_DISABLE, + XE_RTP_ACTION_FLAG(MASKED_REG))) + }, + { XE_RTP_NAME("14014999345"), + XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), STEP(B0, C0)), + XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC, + XE_RTP_ACTION_FLAG(MASKED_REG))) + }, {} }; |