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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2016-10-19 23:48:07 +0300 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2016-11-09 00:40:36 +0300 |
| commit | 47d5c5ffa33d67990c93be14ceb754a89849a3dc (patch) | |
| tree | 64d96f0bd63912a3442a9b5ac4cd8b47884eebb8 | |
| parent | 466e90ca2138c92b1e47d919237488b445b44d73 (diff) | |
| download | linux-47d5c5ffa33d67990c93be14ceb754a89849a3dc.tar.xz | |
ARM: dts: socfpga: Enable QSPI on the Arria5 devkit
Enable the QSPI node and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria5_socdk.dts | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index 3c8867862b0d..f739ead074a2 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -82,6 +82,39 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + &usb1 { status = "okay"; }; |