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author | Clément Léger <cleger@rivosinc.com> | 2023-12-20 18:57:18 +0300 |
---|---|---|
committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-01-10 07:12:26 +0300 |
commit | 5b4d64a819c05e7e96e7ab3f00f4f0967246905f (patch) | |
tree | 98472876f11fd218c6aa26c69b9421a1d68a9a8d | |
parent | 1ec9f381e84877085ed4ce891e89172f8494ddb8 (diff) | |
download | linux-5b4d64a819c05e7e96e7ab3f00f4f0967246905f.tar.xz |
riscv: hwprobe: export Ztso ISA extension
Export the Ztso extension to userspace.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20231220155723.684081-3-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
-rw-r--r-- | Documentation/arch/riscv/hwprobe.rst | 4 | ||||
-rw-r--r-- | arch/riscv/include/uapi/asm/hwprobe.h | 1 | ||||
-rw-r--r-- | arch/riscv/kernel/sys_riscv.c | 1 |
3 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 41463b932268..10bd7b170118 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -161,6 +161,10 @@ The following keys are defined: defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as + defined in the RISC-V ISA manual starting from commit 5618fb5a216b + ("Ztso is now ratified.") + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 91fbe1a7f2e2..01ac3dc196e5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -56,6 +56,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVFH (1 << 30) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) +#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index f0bd7b480b7f..6564fa9e7a7f 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -174,6 +174,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZKSH); EXT_KEY(ZKT); EXT_KEY(ZIHINTNTL); + EXT_KEY(ZTSO); if (has_vector()) { EXT_KEY(ZVBB); |