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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2024-03-21 14:16:40 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-04-21 20:28:49 +0300 |
| commit | 669841a2eff4c0132841dea3ae40d9148a36f257 (patch) | |
| tree | c48def33b09b890ca98bd55d157fb344a56564ab | |
| parent | 27cb9eccf94cb163f9bf3b945f249ab7c42861db (diff) | |
| download | linux-669841a2eff4c0132841dea3ae40d9148a36f257.tar.xz | |
ARM: dts: qcom: sdx55: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-20-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index edc9aaf828c8..68fa5859d263 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -378,6 +378,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie_ep: pcie-ep@1c00000 { |