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authorKevin Cernekee <cernekee@gmail.com>2014-10-21 08:27:57 +0400
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 09:45:11 +0300
commita7ef1eaddbf4bd50bfee92d9dfbecadc61467bbf (patch)
tree05dae8279d0ea3b6bcc6d56a1e99bae5ec9446ce
parent3677a283621446805044a73a36b3539a0b41bc12 (diff)
downloadlinux-a7ef1eaddbf4bd50bfee92d9dfbecadc61467bbf.tar.xz
MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizes
CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c. However, it is currently hardwired to use an L1_SHIFT of 6 (64 bytes). Move the L1_SHIFT selection into the CPU or SoC section so that other SoCs can select different values. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8162/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9ea76ed1c2e4..992f98361e5a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -327,6 +327,7 @@ config MIPS_MALTA
select I8259
select MIPS_BONITO64
select MIPS_CPU_SCACHE
+ select MIPS_L1_CACHE_SHIFT_6
select PCI_GT64XXX_PCI0
select MIPS_MSC
select SWAP_IO_SPACE
@@ -1908,7 +1909,6 @@ config IP22_CPU_SCACHE
config MIPS_CPU_SCACHE
bool
select BOARD_SCACHE
- select MIPS_L1_CACHE_SHIFT_6
config R5000_CPU_SCACHE
bool