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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2024-01-31 10:07:31 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-02-07 01:18:38 +0300 |
| commit | a820a285ef1b7c7fd94055bbb114c0413c04b96b (patch) | |
| tree | 6c074e0a56644eafcae6beeb473890cd5ea72233 | |
| parent | ca8fb2bd2248ae05890c011d691ba5d4a1e7d8d6 (diff) | |
| download | linux-a820a285ef1b7c7fd94055bbb114c0413c04b96b.tar.xz | |
arm64: dts: qcom: sm6115: Fix UFS PHY clocks
QMP PHY used in SM6115 requires 3 clocks:
* ref - 19.2MHz reference clock from RPM
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC
Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-8-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index fc4fbda2be5c..fb067d6c69f6 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1202,8 +1202,12 @@ compatible = "qcom,sm6115-qmp-ufs-phy"; reg = <0x0 0x04807000 0x0 0x1000>; - clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; |